Contributors
A
Engineering Track Poster Accelerating Datapath Verification using Formal techniques
Engineering Track Poster CANCELED - Early IR Drop Prediction using Machine Learning for Power Grid
Engineering Track Poster Learning Box Model using DSO.ai
Engineering Track Poster Quality Assurance of DRC deck by QA Cell Methodology and Automation using Cadence Skill
Engineering Track Poster Credit Based scheduling for Precision time protocol frames in Automotive Ethernet
Engineering Track Poster Credit Based scheduling for Precision time protocol frames in Automotive Ethernet.
Research Manuscript Hybrid Obfuscation of Chiplet-Based Systems
Engineering Track Poster EM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs
Transformative Technologies Theater Revolutionizing EDA: The Power of AI, ML, and NLP
Work-in-Progress Poster Mining SoC Message Flows with Self-Attention
Work-in-Progress Poster A Highly Efficient Reinforcement Learning Based DFG Mapping Method on CGRA
Gladiator Area Poster Battle Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Transformative Technologies Theater The Good, Bad and Cloudy
Front-End Design Adapting to a New Era in Front-End Design and Verification of Power
Engineering Track Poster Automatic Check Generation for Reset States From Design Documents
Front-End Design Design for Verification - Case Reopened
Front-End Design Design for Verification - Case Reopened
Front-End Design A Joint IP XACT/RTL Design Flow for Large SoC
Work-in-Progress Poster Arrow: A Soft RISC-V Vector Accelerator for Machine Learning Inference
Work-in-Progress Poster Arrow: A Soft RISC-V Vector Accelerator for Machine Learning Inference
DAC Pavilion Panel Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Engineering Track Poster Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Research Manuscript Running Software on Embedded Systems: Theory and Practice
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Research Manuscript Leading Developments from the Frontier of High-level Synthesis and Neighborhoods
Research Manuscript Lightning Talk: Latest Trends in Industrial Logic Synthesis
Work-in-Progress Poster Secure Run-Time Hardware Trojan Detection using Lightweight Analytical Models
Research Manuscript Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Work-in-Progress Poster AutoSparse: Automatic Search for Efficient Activation Sparsity-aware CNN Accelerator
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Work-in-Progress Poster APEX: Recommending Design Flow Parameters Using a Variational Autoencoder
Work-in-Progress Poster An ML based Semi-Static Predictor for Approximate Load Value in Cache Memory
Back-End Design Predictive Crosstalk Fixing Using XGBoost Regressor
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Work-in-Progress Poster Optimal ANN-to-SNN Conversion Framework for LSTMs
Work-in-Progress Poster NoNL-DFR: New Model of Digital Delayed Feedback Reservoir without Nonlinear Elements
Engineering Track Poster SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
Work-in-Progress Poster From static analyses to runtime verification of cyber-physical systems
Research Manuscript New Discoveries in Classical Hardware Security Problems
B
Work-in-Progress Poster RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Gladiator Area Poster Battle Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Work-in-Progress Poster Demands for Open-Source Hardware Trojan Detection Tools: An RL Approach
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
DAC Pavilion Panel The Industry 4.0 Revolution of Semiconductor Design
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Engineering Track Poster Addressing Common Verification Pitfalls of Chiplet Interconnects
Special Session (Research) Will Heterogeneous Integration Drive the Next Phase of Moore's Law?
Engineering Track Poster A Digital Emulator for an Analog Continuous Time Sigma Delta Modulator
Front-End Design Low power DAC sub-system for Digital Beam Forming Chip
Engineering Track Poster FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Research Manuscript R-TOSS: A Framework for Real-Time Object Detection using Semi-Structured Pruning
Transformative Technologies Theater Ask Me Anything with Ramki Balasubramaniam
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Engineering Track Poster Design Verification Waveform Analysis through Machine Learning Solution
Back-End Design Hot Hot Chips: Ensuring Stable Power Delivery of an SoC System
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Engineering Track Poster Fast and Reliable IO Ring Checker for Ensuring ESD Robustness and Power Integrity Compliance of SOC design
Engineering Track Poster IO Designs for reliability in advanced technology nodes
Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Work-in-Progress Poster A Computation Interleaving Countermeasure against Profiled Side Channel Attacks
Engineering Track Poster Rethinking the Usage of Self-Contained Reusable Components
Research Manuscript TD-Magic: From Pictures of Timing Diagrams to Formal Specifications
Work-in-Progress Poster Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles
Additional Meeting CANCELLED: Designing for Automotive Functional Safety (FuSa) Requirements
Research Manuscript A Comprehensive Automated Exploration Framework for Systolic Array Designs
Work-in-Progress Poster FlexNAS: Flexible Hardware Aware Training-Less Neural Architecture Search for FPGAs
Engineering Track Poster Intent Based Timing Constraints
Engineering Track Poster Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Research Manuscript Let's Network with Chiplets
Late Breaking Results Poster Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure
Transformative Technologies Theater Alternative approaches to AI chip architectures
Engineering Track Poster Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Work-in-Progress Poster Optimal ANN-to-SNN Conversion Framework for LSTMs
Research Panel Sustainable Autonomous Systems Design
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Engineering Track Poster Aggressor Aware Design for Better IRdrop Results
Work-in-Progress Poster ABC-DE : ABC Design Explorer For LUT-based Synthesis
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Late Breaking Results Poster Late Breaking Results: PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
Engineering Track Poster RV (Reliability Verification) Automation To Improve Execution Efficiency
Engineering Track Poster Intent Based Timing Constraints
Engineering Track Poster Quality Assurance of DRC deck by QA Cell Methodology and Automation using Cadence Skill
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Gladiator Area Poster Battle A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Engineering Track Poster Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Engineering Track Poster Preventing Iterations from SoC Implementation Stage by Developing Pin Accessible Standard Cell Library
Engineering Track Poster Quality Assurance of DRC deck by QA Cell Methodology and Automation using Cadence Skill
Research Manuscript Boosting Neural Networks through Innovative Approximation and Compression
Engineering Track Poster Novel approach to improve the process of register verification in UVM
Engineering Track Poster RV (Reliability Verification) Automation To Improve Execution Efficiency
Work-in-Progress Poster IAM: A Protocol to Improve Security in ISO 15118-20 EV Charging via Remote Attestation
Engineering Track Poster A novel methodology for EM/IR analysis of Complex LDO/Power gated designs.
Embedded Systems and Software MicroFaaS on OpenFaaS: An Embedded Platform for Cloud Functions
DAC Pavilion Panel Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Engineering Track Poster Statistical OCV based Design Closure
Engineering Track Poster Addressing Common Verification Pitfalls of Chiplet Interconnects
Engineering Track Poster Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers
Research Manuscript Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Research Manuscript Global floorplanning via semidefinite programming
Embedded Systems and Software Edge - AI and Security
Research Manuscript AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Special Session (Research) AI Software Is Leading the Hardware Development in Cloud Computing
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Work-in-Progress Poster SoCurity: A Design Approach for Enhancing SoC Security
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Front-End Design A Joint IP XACT/RTL Design Flow for Large SoC
Work-in-Progress Poster CuKnit: Optimized Partitioning of Quantum Circuits using Knitting and Cutting
Hands-On Training Session Increase throughput and productivity with Cadence tools in the cloud using flexible AWS compute choices
Work-in-Progress Poster Improving Block Management in 3D NAND Flash Memory Using Sub-block First Page Write Sequence
Research Manuscript Compiler Optimization for Quantum Computing Using Reinforcement Learning
Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Work-in-Progress Poster SoCurity: A Design Approach for Enhancing SoC Security
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Embedded Systems and Software MicroFaaS on OpenFaaS: An Embedded Platform for Cloud Functions
C
Research Manuscript On EDA-Driven Learning for SAT Solving
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Work-in-Progress Poster FlexNAS: Flexible Hardware Aware Training-Less Neural Architecture Search for FPGAs
Research Manuscript Critical Paths Prediction Under Multiple Corners Based on BiLSTM Network
Work-in-Progress Poster A Discrete 2.5D Chiplet Library and Optimized Mapping of AI Algorithms for Heterogeneous In-memory Acceleration
Research Manuscript Lightning Talk: Bigger and Smarter: Scale up Your AI Accelerators
Engineering Track Poster Is your structural CDC sign-off complete?
Work-in-Progress Poster CTScan: A CGRA-based Platform for Emulation of Power Side-Channel Attacks on CPUs
Work-in-Progress Poster Secure Run-Time Hardware Trojan Detection using Lightweight Analytical Models
Research Manuscript Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
Research Manuscript Adventures in Heterogeneous Computing Systems
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Late Breaking Results Poster Late Breaking Results: PyAIE: A Python-based Programming Framework for Versal ACAP Platforms
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Engineering Track Poster Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
Late Breaking Results Poster Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Gladiator Area Poster Battle Static Analysis for Early Detection and Efficient Debug
Special Session (Research) Predictive analytics for cryogenic CMOS in future quantum computing systems
Research Manuscript IP Protection in Tiny ML
Research Manuscript This is Formal...But You Can Come Casual!
Research Manuscript BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Research Manuscript VideoFlip: Adversarial Bit-Flips for Reducing Video Service Quality
Research Manuscript Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Back-End Design Packaging and Manufacturing Technologies save the day!
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript A Universal Method for Task Allocation on FP-FPS Multiprocessor Systems with Spin Locks
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript Holistic WCRT Analysis for Global Fixed-Priority Preemptive Multiprocessor Scheduling
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints
Research Manuscript Any-Angle Routing for Redistribution Layers in 2.5D IC Packages
Research Manuscript Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints
Research Manuscript Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology
Late Breaking Results Poster Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Research Manuscript APP: enabling soft real-time execution on densely-populated hybrid memory systems
Work-in-Progress Poster ProHash: A Promotion-based Hashing Index Scheme for NVM-based Systems
Work-in-Progress Poster CANCELED - Interleaving-Mapping: A Novel Data Layout in SPRAM
Engineering Track Poster SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Work-in-Progress Poster ProHash: A Promotion-based Hashing Index Scheme for NVM-based Systems
Research Manuscript Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Special Session (Research) Cloud and Edge: New Age of Automotive Computing
Research Manuscript AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators
Research Manuscript Lightning Talk: The Next Wave of High-level Synthesis
Special Session (Research) The Design of Next-Generation Cloud Computing Systems
Engineering Track Poster Power Integrity analysis of 3D stacking Structure in CMOS Image Sensor Chip
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints
Research Manuscript Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints
Research Manuscript Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints
Research Manuscript PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration
Research Manuscript Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Work-in-Progress Poster CANCELED - Towards Large-Scale Routing: A Novel Learning Based Divide & Merge Approach
Work-in-Progress Poster AMACC: Asynchronous Memory Access Accelerator for RISC-V Embedded Soft Processors
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Work-in-Progress Poster MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Research Manuscript FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
Late Breaking Results Poster Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Work-in-Progress Poster ProHash: A Promotion-based Hashing Index Scheme for NVM-based Systems
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Research Manuscript DriverJar: Lightweight Device Driver Isolation for ARM
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Research Manuscript Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Research Manuscript Lightning Talk: Architecture Solutions for Emerging Memory Based Storage and Computing to Achieve High Yield and Low Error Rate
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript Critical Paths Prediction Under Multiple Corners Based on BiLSTM Network
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Research Manuscript Route Me if You Can!
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Research Manuscript Lightning Talk: The Need for and Challenges of Heterogeneous Systems
Special Session (Research) Moving the Center of Cloud Servers from Processors to IPUs
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Engineering Track Poster Low Power DTCO of FINFET Logic Process for Stacked CMOS Image Sensor
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Engineering Track Poster Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Research Manuscript AVX Timing Side-Channel Attacks against Address Space Layout Randomization*
Late Breaking Results Poster Late Breaking Results: PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Late Breaking Results Poster Late Breaking Results: RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network
Engineering Track Poster Learning Box Model using DSO.ai
Work-in-Progress Poster A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Work-in-Progress Poster LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage
Back-End Design Over-Design Methodology for Operating Voltage Minimization
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Research Manuscript Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
Research Manuscript Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
Back-End Design Over-Design Methodology for Operating Voltage Minimization
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Gladiator Area Poster Battle Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Research Manuscript Any-Angle Routing for Redistribution Layers in 2.5D IC Packages
Research Manuscript BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing
Research Manuscript AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing
Work-in-Progress Poster Quickloop: An efficient, FPGA-accelerated exploration of parameterized RTL generators
Research Manuscript Any-Angle Routing for Redistribution Layers in 2.5D IC Packages
Work-in-Progress Poster Near-Memory Computing with Compressed Embedding Table for Personalized Recommendation
Work-in-Progress Poster CR2: A Compressed ReRAM-based DNN Accelerator by Combining Computation and Read operation
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Research Manuscript Ever more optimized simulations of fermionic systems on a quantum computer
Work-in-Progress Poster RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Research Manuscript Formal Verification of Restoring Dividers made Fast and Simple
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Research Manuscript A Comprehensive Automated Exploration Framework for Systolic Array Designs
Work-in-Progress Poster FlexNAS: Flexible Hardware Aware Training-Less Neural Architecture Search for FPGAs
Research Manuscript Lightning Talk: Scaling Up Quantum Compilation -- Challenges and Opportunities
Research Manuscript Rubick: A Synthesis Framework For Spatial Architectures via Dataflow Decomposition
Research Manuscript Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Research Manuscript Automating Constraint-Aware Datapath Optimization using E-Graphs
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Embedded Systems and Software MicroFaaS on OpenFaaS: An Embedded Platform for Cloud Functions
DAC Pavilion Panel Ask Me Anything with Joe Costello and Wally Rhines
Research Manuscript Automating Constraint-Aware Datapath Optimization using E-Graphs
Research Manuscript Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript FSD: A Fast Secure Deletion Strategy for High-Density Flash Memories through WOM-v Codes
Work-in-Progress Poster Move-On-Cover: An Efficient Secure Deletion Strategy for Interlaced Magnetic Recording
Research Manuscript Faster and stronger Lossless Compression with Optimized Autoregressive framework
Engineering Track Poster CANCELED - Tips & Facts That Every Design Engineer Should Know About RTL Synthesis
Engineering Track Poster A Multiphysics Simulation Flow for High Performance MMIC Products for Power 5G and RF Applications
Analyst Presentation The AI Hardware Show Live: Silicon or Survival
Transformative Technologies Theater Enabling AI at Zettascale: Wafers, Chiplets, or both?
D
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Research Manuscript An Efficient Accelerator for Point-based and Voxel-based Point Cloud Neural Networks
Research Manuscript Memory-Efficient and Real-Time SPAD-based dToF Imaging with Spatial and Statistical Correlation
Work-in-Progress Poster Fuzzing and Static Analysis Guided Symbolic Execution to Detect Hardware Trojans
Research Manuscript Efficient Transformer Inference with Statically Structured Sparse Attention
Work-in-Progress Poster Efficient Accelerator Integration with Generated Modules
Work-in-Progress Poster FuseDM: Accelerating Diffusion Model Sampling on Versal ACAP Architecture
Engineering Track Poster RV (Reliability Verification) Automation To Improve Execution Efficiency
Research Manuscript Discerning the Limitations of GNN-based Attacks on Logic Locking
Gladiator Area Poster Battle Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Special Session (Research) Technological Advancements in the Quantum space – from Hardware Architecture to Computing Platform
Back-End Design Packaging and Manufacturing Technologies save the day!
Engineering Track Poster Accelerating Datapath Verification using Formal techniques
Research Manuscript Formal Verification of Restoring Dividers made Fast and Simple
Work-in-Progress Poster Optimal ANN-to-SNN Conversion Framework for LSTMs
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Work-in-Progress Poster A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Work-in-Progress Poster A cost-generic logic synthesis framework with customizable cost functions
Research Manuscript Breaking news from RTL technology-independent optimization
Work-in-Progress Poster CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Engineering Track Poster Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
Engineering Track Poster Accelerating Datapath Verification using Formal techniques
Front-End Design Debug Accelerator & Performance Validator
Engineering Track Poster SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Engineering Track Poster SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Work-in-Progress Poster A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Engineering Track Poster A Machine Learning Approach Towards SKILL Code Autocompletion
Work-in-Progress Poster Optimal ANN-to-SNN Conversion Framework for LSTMs
Work-in-Progress Poster Static Program Analysis against Risky IoT Interaction in Zero Knowledge Settings
Work-in-Progress Poster RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Transformative Technologies Theater Unleashing Semiconductor Innovation by Fostering Resilient Ecosystems
Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Work-in-Progress Poster A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Transformative Technologies Theater Alternative approaches to AI chip architectures
Engineering Track Poster Advanced Node PPA and Design Optimization Using Cerebrus ML Flow
Work-in-Progress Poster Secure Run-Time Hardware Trojan Detection using Lightweight Analytical Models
Engineering Track Poster Intent Based Timing Constraints
Research Manuscript Condense: A Framework for Device and Frequency Adaptive Neural Network Models on the Edge
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Research Manuscript Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Research Manuscript PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment
Research Manuscript Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Work-in-Progress Poster CANCELED - Towards Large-Scale Routing: A Novel Learning Based Divide & Merge Approach
Engineering Track Poster Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Work-in-Progress Poster Real-time Deep Visual Tracking on a Tight Budget
Engineering Track Poster A Statistical approach to identify wasted power consumption in combinational clusters
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Research Manuscript CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Research Manuscript BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs
Research Manuscript Fast but Not Precarious: Meeting Efficiency Challenges in Autonomous Systems
Research Manuscript Reaction Time Analysis of Event-Triggered Processing Chains with Data Refreshing
Engineering Track Poster CANCELED - Early IR Drop Prediction using Machine Learning for Power Grid
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript Accelerating DNN Inference with Heterogeneous Multi-DPU Engines
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Engineering Track Poster RV (Reliability Verification) Automation To Improve Execution Efficiency
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Research Panel Is Deep Learning Computationally Sustainable?
Work-in-Progress Poster CANCELED - Interleaving-Mapping: A Novel Data Layout in SPRAM
Research Manuscript The Path to Reliable, Secure, and Energy-efficient Cloud-edge Continuum
Research Manuscript Lightning Talk - The New Era of Cognitive Computational Intelligence
Research Manuscript SimLL: Similarity-Based Logic Locking against Machine Learning Attacks
Work-in-Progress Poster Zero Trust Verification of Third Party IPs with Secure Multiparty Computing
Engineering Track Poster Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Gladiator Area Poster Battle Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs
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Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Work-in-Progress Poster Arrow: A Soft RISC-V Vector Accelerator for Machine Learning Inference
Engineering Track Poster Rethinking the Usage of Self-Contained Reusable Components
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Additional Meeting Uncovering Blind Spots: Reliability Monitoring of Chiplet-Based Designs
Special Session (Research) Vehicle as a Cache - Edge Computing for Automated Data Centric Vehicles
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
Research Manuscript Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
Research Manuscript UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
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Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Engineering Track Poster A Statistical approach to identify wasted power consumption in combinational clusters
Transformative Technologies Theater Enabling AI at Zettascale: Wafers, Chiplets, or both?
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Work-in-Progress Poster LUNAR: A Native Table Engine for IoT Devices
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Research Manuscript When Bio-inspired Models Met Hardware Optimization
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Research Manuscript Don’t Cross Me! Cross-layer System Security
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
Research Manuscript CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays
Research Manuscript Fair Will Go On: A Collaboration-Aware Fairness Scheme for NVMe SSD in Cloud Storage System
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
Work-in-Progress Poster L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Work-in-Progress Poster FlexNAS: Flexible Hardware Aware Training-Less Neural Architecture Search for FPGAs
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Research Manuscript Best Machine Learning Session In-(Recent)-Memory
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Engineering Track Poster Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Back-End Design Why the Delay? Enabling Time
Work-in-Progress Poster L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Research Manuscript "Know Thy Self, Know Thy Enemy: HW Security Attacks and Defenses"
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Engineering Track Poster Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Work-in-Progress Poster CANCELED - SecGraph: Security Oriented Graph NeuRal Network Assisted Protection on Hardware
Research Panel Why is Curvy Design an Opportunity Now?
DAC Pavilion Panel Ask Me Anything with Joe Costello and Wally Rhines
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Work-in-Progress Poster ABC-DE : ABC Design Explorer For LUT-based Synthesis
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Special Session (Research) Novel Algorithms and Architectures for Long Read Sequence Analysis
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Research Manuscript Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Research Manuscript ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Research Manuscript Lightning Talk - ML for EDA: Hype or Reality?
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Research Manuscript Efficient Transformer Inference with Statically Structured Sparse Attention
Engineering Track Poster Special Bit Pattern Injection in Simulation Verification by leveraging Formal Verification
Research Manuscript Expanding Compute-in-Memory for Emerging Machine Learning
Research Manuscript Accelerators, Accelerators and More Accelerators!
Research Manuscript Lightning Talk: The Accelerator Landscape - A System-Level Perspective
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Research Manuscript AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Research Manuscript ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks
Front-End Design Verification Beyond Coverage
Engineering Track Poster Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++
Research Manuscript Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Gladiator Area Poster Battle Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Engineering Track Poster Paradigm Shift in Power Aware Simulation Using Formal Techniques
Gladiator Area Poster Battle Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis
Front-End Design Design for Verification - Case Reopened
Front-End Design The Next Frontiers in the Front End
Engineering Track Poster A novel methodology for EM/IR analysis of Complex LDO/Power gated designs.
Research Manuscript Chiplets: How Small is too Small?
RISC-V Zone Codasip's Data Driven Design Methodology Part 1
RISC-V Zone Codasip's Data Driven Design Methodology Part 2
Front-End Design Verification Beyond Coverage
Work-in-Progress Poster CANCELED - A Processing Element for Sparse Tensor Accelerators
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Special Session (Research) Unleashing Side-channel Power Estimation Super Powers
Research Manuscript TD-Magic: From Pictures of Timing Diagrams to Formal Specifications
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Research Manuscript Reaction Time Analysis of Event-Triggered Processing Chains with Data Refreshing
Engineering Track Poster Camelus: Scalable and Generic SIMD Programming for AI Accelerators
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Research Manuscript An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
Engineering Track Poster Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Research Manuscript NASA in DAC?
Engineering Track Poster Novel Chip-Package-System thermal analysis with RTL Power
Research Manuscript ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Research Manuscript "Know Thy Self, Know Thy Enemy: HW Security Attacks and Defenses"
Work-in-Progress Poster CANCELED - SecGraph: Security Oriented Graph NeuRal Network Assisted Protection on Hardware
Work-in-Progress Poster Zero Trust Verification of Third Party IPs with Secure Multiparty Computing
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Engineering Track Poster Intent Based Timing Constraints
Engineering Track Poster Statistical OCV based Design Closure
DAC Pavilion Panel The Industry 4.0 Revolution of Semiconductor Design
Engineering Track Poster Statistical OCV based Design Closure
Research Manuscript Chiplets: How Small is too Small?
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Engineering Track Poster Is your structural CDC sign-off complete?
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Engineering Track Poster Considerations for Accelerating and Efficient Use of Chip Design in the Cloud
Back-End Design ML Based DRV Prediction and Optimization for DTCO
Research Manuscript Lightning Talk: How to Boost Deep Neural Networks for Computer Vision
Work-in-Progress Poster A Novel Sensor Fusion Technique for 2D Object Detection for Self-Driving Cars
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Work-in-Progress Poster A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Work-in-Progress Poster Analog System High-level Synthesis to Physical Devices
Embedded Systems and Software Edge - AI and Security
Front-End Design Verification Beyond Coverage
DAC Pavilion Panel The Industry 4.0 Revolution of Semiconductor Design
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Research Manuscript Timing-critical Design and Analysis
Research Manuscript Contention-Free Configured Grant Scheduling for 5G URLLC Traffic
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Research Manuscript APPEND: Towards Application Enhanced NPU Designing
Research Manuscript FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
Special Session (Research) Federated Learning and Analysis with Multi-access Edge Computing for Connected and Automated Vehicles
Work-in-Progress Poster Analog System High-level Synthesis to Physical Devices
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Work-in-Progress Poster A Highly Efficient Reinforcement Learning Based DFG Mapping Method on CGRA
Engineering Track Poster The anatomy of incremental floorplanning solutions
Front-End Design Dragging Debug into a New Era
Work-in-Progress Poster Node-level Dynamic Distributed Trust Metric Evaluation
Work-in-Progress Poster Novel Adaptive Quantization Methodology for 8-bit Floating-Point DNN Training
Engineering Track Poster Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript TD-Magic: From Pictures of Timing Diagrams to Formal Specifications
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Engineering Track Poster MathLib - Math functions Library for SystemVerilog/UVM
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Late Breaking Results Poster Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure
Engineering Track Poster Capturing Statistical Characteristics of High-Sigma Reliability Analysis Methods
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Front-End Design Crossing the RISC-V customization barrier with formal
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
Research Manuscript Learning with Drives and Convertibles - from Near Data to Cloud
Transformative Technologies Theater The Good, Bad and Cloudy
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Work-in-Progress Poster SEASONS: Signal and Energy Aware Sensing on iNtermittent Systems
Late Breaking Results Poster Late Breaking Results: From Hybrid Design Automation for Field-coupled Nanotechnologies
Hands-On Training Session Build a Cadence Burst-to-Cloud workflow with NetApp “Design Anywhere” on AWS
Research Manuscript Lightning Talk - Don’t Cross Me! Cross-layer System Security
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Late Breaking Results Poster Late Breaking Results: PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Late Breaking Results Poster Late Breaking Results: RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network
Research Manuscript A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Research Manuscript Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Work-in-Progress Poster CR2: A Compressed ReRAM-based DNN Accelerator by Combining Computation and Read operation
Engineering Track Poster 3DIC Design floorplanning flow and Early Area Estimation for Area optimization
Engineering Track Poster SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Work-in-Progress Poster Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Work-in-Progress Poster SoCurity: A Design Approach for Enhancing SoC Security
Research Manuscript ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Engineering Track Poster Novel Chip-Package-System thermal analysis with RTL Power
Engineering Track Poster Multi-Policy Lint Signoff for SoCs
Research Manuscript Intermittent-Aware Neural Network Pruning
Research Manuscript Rethinking Programming Frameworks for In-Storage Processing
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Work-in-Progress Poster NeuroPDR: Integrating Neural Networks in PDR Algorithm for Hardware Model Checking
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Research Manuscript DRPTM: A Decoupled Read-efficient High-scalable Persistent Transactional Memory
Research Manuscript Lightning Talk: Power and Performance Reconciliation -- from Tradeoff to Win-Win
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Special Session (Research) Design the Clouds: Acceleration, Interconnect, and Infrastructure
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Research Manuscript Contention-Free Configured Grant Scheduling for 5G URLLC Traffic
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Engineering Track Poster Camelus: Scalable and Generic SIMD Programming for AI Accelerators
Research Manuscript BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Research Manuscript A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
Research Manuscript Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Work-in-Progress Poster MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Work-in-Progress Poster Context-Aware Runtime Model Reconfiguration for Energy-Efficient Autonomous Vehicle Perception
Research Manuscript DistHD: A Learner-Aware Encoding Method for Hyperdimensional Classification
Late Breaking Results Poster Late Breaking Results: PyAIE: A Python-based Programming Framework for Versal ACAP Platforms
Late Breaking Results Poster Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection
Work-in-Progress Poster MicroNAS: Zero-shot Neural Architecture Search for MCUs
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Special Session (Research) Advanced Packaging Design Challenges for Heterogeneous Integration
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Late Breaking Results Poster Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly
Work-in-Progress Poster RODOS: Robust Design Optimization with Simulator Learning
I
Research Manuscript HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Research Manuscript Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Work-in-Progress Poster Analog System High-level Synthesis to Physical Devices
Work-in-Progress Poster NoNL-DFR: New Model of Digital Delayed Feedback Reservoir without Nonlinear Elements
Research Manuscript A Farewell to the Numerical Computing Paradigm
Research Manuscript BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-parallel Modular Multiplication
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
Research Manuscript Comprehensive Integration of Hyperdimensional Computing with Deep Learning towards Neuro-Symbolic AI
Research Manuscript DistHD: A Learner-Aware Encoding Method for Hyperdimensional Classification
Late Breaking Results Poster Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection
Research Manuscript Lightning Talk - Bridging Neuro-Dynamics and Cognition
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Engineering Track Poster Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Late Breaking Results Poster Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection
Research Manuscript Hybrid Obfuscation of Chiplet-Based Systems
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Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Engineering Track Poster SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
Work-in-Progress Poster Graph Machine Learning assisted Analog Circuit Designing
Engineering Track Poster A Statistical approach to identify wasted power consumption in combinational clusters
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Engineering Track Poster Addressing Common Verification Pitfalls of Chiplet Interconnects
Engineering Track Poster Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Engineering Track Poster CANCELED - Auto-Detection and Unraveling the reasons for the Unoptimized Nets
Work-in-Progress Poster Demands for Open-Source Hardware Trojan Detection Tools: An RL Approach
Research Manuscript BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems
Work-in-Progress Poster Leveraging the Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators
Research Manuscript Lightning Talk: Architecture 2.0
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Engineering Track Poster Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
Research Manuscript AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Research Manuscript VideoFlip: Adversarial Bit-Flips for Reducing Video Service Quality
Research Manuscript Let's Get with the Processing-in-Memory Program
Transformative Technologies Theater Ask Me Anything with Sean Jensen-Grey
Work-in-Progress Poster Machine learning based design methodology for power optimization of wide range SRAM
Late Breaking Results Poster Late Breaking Results: PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Late Breaking Results Poster Late Breaking Results: RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network
Work-in-Progress Poster Spike-Predictable Neuron Circuits with Adaptive Threshold for Low-power SNN Systems
Work-in-Progress Poster GEBA: Gradient-Error-Based Approximation of Activation Functions
Work-in-Progress Poster Machine learning based design methodology for power optimization of wide range SRAM
Back-End Design Over-Design Methodology for Operating Voltage Minimization
Front-End Design Emulation Based Automation Platform For SoC Performance Verification
Gladiator Area Poster Battle Novel Hierarchical IREM Sign-off Flow using ROM
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
Work-in-Progress Poster A CNN-Based Code Assistance for Layout-to-Generator Conversion of Analog Circuits
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Research Manuscript UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Research Manuscript Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration
Work-in-Progress Poster Rectification Learning From Hypotheses Refutation and Relevance Classification
Research Manuscript PRIMER: A Privacy-Preserving Transformer on Encrypted Data
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Research Manuscript HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Work-in-Progress Poster A RISC-V Instruction Level Acceleration for FFT
Research Manuscript Battle Against Fluctuating Quantum Noise: Compression-Aided Framework to Enable Robust Quantum Neural Network
Research Manuscript Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
Research Manuscript On-Device Unsupervised Image Segmentation
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript PSMiner: A Pattern-Aware Accelerator for High-Performance Streaming Graph Pattern Mining
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Work-in-Progress Poster CANCELED - SecGraph: Security Oriented Graph NeuRal Network Assisted Protection on Hardware
Research Manuscript Accelerating Sparse LU Factorization with Density-aware Adaptive Matrix Multiplication for Circuit Simulation
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Research Manuscript New Waves of Boosting Power Efficiency
Engineering Track Poster Correct by construction layout design by auto device placement
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Research Manuscript Best Machine Learning Session In-(Recent)-Memory
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Transformative Technologies Theater The Good, Bad and Cloudy
Transformative Technologies Theater Simplifying Success in the Cloud
Back-End Design Thermal Aware On-Die Electrical Analysis
Transformative Technologies Theater Alternative approaches to AI chip architectures
Embedded Systems and Software Defining Avionics System Architecture For Multiple Use Cases With Stringent Requirements Using System Modelling
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Special Session (Research) Predictive analytics for cryogenic CMOS in future quantum computing systems
Gladiator Area Poster Battle High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
Research Manuscript An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Work-in-Progress Poster Zero Trust Verification of Third Party IPs with Secure Multiparty Computing
Embedded Systems and Software Early Android Software Verification With RISC-V Virtual Platforms
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Work-in-Progress Poster CTScan: A CGRA-based Platform for Emulation of Power Side-Channel Attacks on CPUs
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
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Research Manuscript Lightning Talk: Advancing Placement: An Updated Challenges List
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Research Panel Why is Curvy Design an Opportunity Now?
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Engineering Track Poster Optimal MSCTS Driver duplication for improved H-Tree Clock Skew and Insertion delay
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
Back-End Design Design Data Browser (DDB) A High-Performance Interactive Environment for Timing Triage
Engineering Track Poster Intent Based Timing Constraints
United States of America
Work-in-Progress Poster Spike-Predictable Neuron Circuits with Adaptive Threshold for Low-power SNN Systems
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Engineering Track Poster 3D IC Inter-Die Test Implementation Using IEEE1838
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Front-End Design Full SoC power analysis and estimation with end-user software early in the design cycle
Engineering Track Poster Learning Box Model using DSO.ai
Research Manuscript Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
Engineering Track Poster Bridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics Designs
Research Manuscript ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks
Gladiator Area Poster Battle Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Research Manuscript Lightning Talk - NASA in DAC?
Engineering Track Poster Electrical Analysis using Hierarchical Approach On Ultra Large Designs
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Transformative Technologies Theater Cloud but not for Compute - A New Paradigm for Open IC Design
Back-End Design Packaging and Manufacturing Technologies save the day!
Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Research Manuscript Discerning the Limitations of GNN-based Attacks on Logic Locking
Work-in-Progress Poster APEX: Recommending Design Flow Parameters Using a Variational Autoencoder
Back-End Design Physical Design Challenges Manifested
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Research Manuscript CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Transformative Technologies Theater Alternative approaches to AI chip architectures
Research Manuscript Efficient Transformer Inference with Statically Structured Sparse Attention
Research Manuscript GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs
Research Panel Is Deep Learning Computationally Sustainable?
Late Breaking Results Poster Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Engineering Track Poster Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
Work-in-Progress Poster DeepSeq: Deep Sequential Circuit Learning
Research Manuscript On EDA-Driven Learning for SAT Solving
Research Manuscript Lightning Talk: A Perspective on Formal Verification
Work-in-Progress Poster Fornax: Lightweight Energy-Efficient DNN Accelerator Architecture for Edge Devices
Work-in-Progress Poster Wear Leveling of Processing Elements Array in Deep Neural Network Accelerators
Work-in-Progress Poster A CNN-Based Code Assistance for Layout-to-Generator Conversion of Analog Circuits
Work-in-Progress Poster ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging
Work-in-Progress Poster RODOS: Robust Design Optimization with Simulator Learning
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Work-in-Progress Poster Wear Leveling of Processing Elements Array in Deep Neural Network Accelerators
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Engineering Track Poster Learning Box Model using DSO.ai
Engineering Track Poster Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Engineering Track Poster Learning Box Model using DSO.ai
Special Session (Research) CUDA Quantum: The Platform for Integrated Quantum-Classical Computing
Engineering Track Poster 3DIC Design floorplanning flow and Early Area Estimation for Area optimization
Work-in-Progress Poster ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Work-in-Progress Poster A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
Engineering Track Poster Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Work-in-Progress Poster A CNN-Based Code Assistance for Layout-to-Generator Conversion of Analog Circuits
Engineering Track Poster Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Engineering Track Poster 3DIC Design floorplanning flow and Early Area Estimation for Area optimization
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Engineering Track Poster Considerations for Accelerating and Efficient Use of Chip Design in the Cloud
Engineering Track Poster Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Work-in-Progress Poster Spike-Predictable Neuron Circuits with Adaptive Threshold for Low-power SNN Systems
Research Manuscript A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Work-in-Progress Poster AutoSparse: Automatic Search for Efficient Activation Sparsity-aware CNN Accelerator
Late Breaking Results Poster Late Breaking Results: PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Research Manuscript AVX Timing Side-Channel Attacks against Address Space Layout Randomization*
Engineering Track Poster Path Tracer for Tr.-level STA Setup using Synopsys NanoTime
Engineering Track Poster Considerations for Accelerating and Efficient Use of Chip Design in the Cloud
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Work-in-Progress Poster Near-Memory Computing with Compressed Embedding Table for Personalized Recommendation
Research Manuscript Not Fast Enough? Hardware Acceleration for Transformers and Beyond
Work-in-Progress Poster A Novel Sensor Fusion Technique for 2D Object Detection for Self-Driving Cars
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Research Manuscript Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Engineering Track Poster SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Research Manuscript Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment
Research Manuscript Timing-critical Design and Analysis
Work-in-Progress Poster Near-Memory Computing with Compressed Embedding Table for Personalized Recommendation
Engineering Track Poster Correct by construction layout design by auto device placement
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Hands-On Training Session Build a Cadence Burst-to-Cloud workflow with NetApp “Design Anywhere” on AWS
Work-in-Progress Poster Fornax: Lightweight Energy-Efficient DNN Accelerator Architecture for Edge Devices
Engineering Track Poster CANCELED - Auto-Detection and Unraveling the reasons for the Unoptimized Nets
Work-in-Progress Poster Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Research Manuscript AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Research Manuscript Lightning Talk - "ML under Attack, and ML for Attacks and Defenses"
Research Panel Lost in Silicon: The Need for Re-Innovating the Future of Trusted Hardware and Supply Chain Resilience
Work-in-Progress Poster Near-Memory Computing with Compressed Embedding Table for Personalized Recommendation
Research Manuscript VideoFlip: Adversarial Bit-Flips for Reducing Video Service Quality
Research Manuscript ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Embedded Systems and Software Using ChatGPT and OpenAI to Write Embedded Software>
Work-in-Progress Poster Rectification Learning From Hypotheses Refutation and Relevance Classification
Work-in-Progress Poster How connection delay can affect synchronization with two-factor tools
Engineering Track Poster Is your structural CDC sign-off complete?
Work-in-Progress Poster CuKnit: Optimized Partitioning of Quantum Circuits using Knitting and Cutting
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
DAC Pavilion Panel Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Engineering Track Poster Statistical OCV based Design Closure
Engineering Track Poster Statistical OCV based Design Closure
Special Session (Research) Buried Power Rails
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Engineering Track Poster Statistical IR Analysis with Ansys SigmaDvD
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Research Manuscript ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Research Manuscript Discerning the Limitations of GNN-based Attacks on Logic Locking
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Engineering Track Poster IO Designs for reliability in advanced technology nodes
Engineering Track Poster Advanced Node PPA and Design Optimization Using Cerebrus ML Flow
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Engineering Track Poster IO Designs for reliability in advanced technology nodes
Engineering Track Poster A Statistical approach to identify wasted power consumption in combinational clusters
Work-in-Progress Poster Graph Machine Learning assisted Analog Circuit Designing
Research Manuscript Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Engineering Track Poster Accelerating Datapath Verification using Formal techniques
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Research Manuscript APP: enabling soft real-time execution on densely-populated hybrid memory systems
Research Manuscript Intermittent-Aware Neural Network Pruning
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Engineering Track Poster Learning Box Model using DSO.ai
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Engineering Track Poster Advanced transceiver components for robust handling of signal noise and loss
Research Manuscript Let’s Go Fast - DNN Acceleration!
L
Front-End Design Verification Beyond Coverage
Research Manuscript On EDA-Driven Learning for SAT Solving
Engineering Track Poster Design Verification Waveform Analysis through Machine Learning Solution
Work-in-Progress Poster CANCELED - A Unifying Tensor View for Lightweight CNNs
Work-in-Progress Poster Real-time Deep Visual Tracking on a Tight Budget
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Work-in-Progress Poster A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
Gladiator Area Poster Battle Novel Hierarchical IREM Sign-off Flow using ROM
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Research Manuscript A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Research Manuscript A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Work-in-Progress Poster ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging
Front-End Design Emulation Based Automation Platform For SoC Performance Verification
Back-End Design Over-Design Methodology for Operating Voltage Minimization
Research Manuscript Fantastic AI System Improvements and Where to Find Them
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Work-in-Progress Poster A Novel Sensor Fusion Technique for 2D Object Detection for Self-Driving Cars
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Work-in-Progress Poster Machine learning based design methodology for power optimization of wide range SRAM
Engineering Track Poster 3D IC Inter-Die Test Implementation Using IEEE1838
Research Manuscript Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
Research Manuscript A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Work-in-Progress Poster A cost-generic logic synthesis framework with customizable cost functions
Work-in-Progress Poster CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Engineering Track Poster Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++
Engineering Track Poster Hierarchical Power Grid Analysis for 3D-IC
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Gladiator Area Poster Battle HW Security Path Validation Using Formal Methods: Intel Case Studies
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Research Manuscript APPEND: Towards Application Enhanced NPU Designing
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Research Manuscript Dear Accelerator, Could You Please Be More Specific?
Research Manuscript HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Research Manuscript APPEND: Towards Application Enhanced NPU Designing
Work-in-Progress Poster CANCELED - A Unifying Tensor View for Lightweight CNNs
Research Manuscript Faster and stronger Lossless Compression with Optimized Autoregressive framework
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Work-in-Progress Poster VSAGE: an End-to-End Automated VCO-based ΔΣ ADC Generator
Research Manuscript FIONA: Fine-grained Incoherent Optical DNN Accelerator Search Towards Superior Efficiency and Robustness
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript Multi-accelerator and Distributed System for ML
Work-in-Progress Poster DeepSeq: Deep Sequential Circuit Learning
Research Manuscript On EDA-Driven Learning for SAT Solving
Research Manuscript Ever more optimized simulations of fermionic systems on a quantum computer
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript Optimal Synthesis of Multi-Controlled Qudit Gates
Work-in-Progress Poster VSAGE: an End-to-End Automated VCO-based ΔΣ ADC Generator
Work-in-Progress Poster CANCELED - Interleaving-Mapping: A Novel Data Layout in SPRAM
Work-in-Progress Poster A RISC-V Instruction Level Acceleration for FFT
Research Manuscript Global floorplanning via semidefinite programming
Research Manuscript EENet: Energy Efficient Neural Networks with Run-time Power Management
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Work-in-Progress Poster DAG-aware Synthesis Orchestration
Research Manuscript Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks*
Research Manuscript Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Work-in-Progress Poster CANCELED - Multi-objective optimization for Floating Point Mix-Precision Tuning
Research Manuscript FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Work-in-Progress Poster Static Program Analysis against Risky IoT Interaction in Zero Knowledge Settings
Late Breaking Results Poster Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Research Manuscript PROPHET: Predictive On-Chip Power Meter for Hardware DNN Accelerator
Research Manuscript DRPTM: A Decoupled Read-efficient High-scalable Persistent Transactional Memory
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Work-in-Progress Poster ProHash: A Promotion-based Hashing Index Scheme for NVM-based Systems
Research Manuscript A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
Work-in-Progress Poster FSMGen: Bridging High-Level Specification and Low-Level Hardware Construction on FPGAs
Work-in-Progress Poster MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript On a Moreau Envelope Wirelength Model for Analytical Global Placement
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Gladiator Area Poster Battle Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Work-in-Progress Poster Near-Memory Computing with Compressed Embedding Table for Personalized Recommendation
Engineering Track Poster SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
Special Session (Research) Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps
Research Manuscript Glass Interposer Integration of Logic and Memory Chiplets: PPA and Signal/Power Integrity Benefits
Work-in-Progress Poster Fornax: Lightweight Energy-Efficient DNN Accelerator Architecture for Edge Devices
Work-in-Progress Poster Wear Leveling of Processing Elements Array in Deep Neural Network Accelerators
Engineering Track Poster Novel Chip-Package-System thermal analysis with RTL Power
Research Manuscript Intermittent-Aware Neural Network Pruning
Research Panel CHIPS & SCIENCE & EDA: A New (and Amplified) Future?
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Work-in-Progress Poster CANCELED - A Unifying Tensor View for Lightweight CNNs
Research Manuscript Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Research Manuscript All Routes to Timing Closure
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Research Manuscript On a Moreau Envelope Wirelength Model for Analytical Global Placement
Research Manuscript Unleashing the Power of Neural Networks through Hardware Acceleration
Special Session (Research) Cross-Layer Innovations for Enabling Real-Time and Efficient Eye Tracking in VR/AR
Research Manuscript Instant-NeRF: Instant On-Device Neural Radiance Field Training via Algorithm-Accelerator Co-Designed Near-Memory Processing
Research Manuscript Lightning Talk - "Making AI Smarter, Faster, and More Efficient": Current Approaches and Looking into the Future
Research Manuscript Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Work-in-Progress Poster CANCELED - Interleaving-Mapping: A Novel Data Layout in SPRAM
Engineering Track Poster SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Research Manuscript Intermittent-Aware Neural Network Pruning
Research Manuscript HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Research Manuscript HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript IP Protection in Tiny ML
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript On a Moreau Envelope Wirelength Model for Analytical Global Placement
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Research Manuscript EDGE: Efficient DAG-based Global Routing Engine
Research Manuscript Route Me if You Can!
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Research Manuscript Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Work-in-Progress Poster Latency-Bounded Clock Mesh Synthesis Methodology Based on Dynamic Programming
Work-in-Progress Poster DAG-aware Synthesis Orchestration
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Work-in-Progress Poster Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Research Manuscript FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Research Manuscript Rethinking AIG Resynthesis in Parallel*
Research Manuscript A High-accurate Multi-objective Exploration Framework for Design Space of CPU
Research Manuscript Accelerating Sparse LU Factorization with Density-aware Adaptive Matrix Multiplication for Circuit Simulation
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Research Manuscript Boosting Neural Networks through Innovative Approximation and Compression
Work-in-Progress Poster Static Program Analysis against Risky IoT Interaction in Zero Knowledge Settings
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Research Manuscript Rethinking Programming Frameworks for In-Storage Processing
Work-in-Progress Poster Optimal ANN-to-SNN Conversion Framework for LSTMs
Work-in-Progress Poster Zero Trust Verification of Third Party IPs with Secure Multiparty Computing
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Special Session (Research) Advanced Packaging and Integration: It's Not Enough
Research Manuscript PRIMER: A Privacy-Preserving Transformer on Encrypted Data
Work-in-Progress Poster From static analyses to runtime verification of cyber-physical systems
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Research Manuscript ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
Engineering Track Poster Layout Proximity Effect On Interconnect Capacitance
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Work-in-Progress Poster AMACC: Asynchronous Memory Access Accelerator for RISC-V Embedded Soft Processors
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Research Manuscript Lightning Talk - Bringing Together Foundation Models and Edge Devices
Work-in-Progress Poster Efficient Accelerator Integration with Generated Modules
Work-in-Progress Poster FuseDM: Accelerating Diffusion Model Sampling on Versal ACAP Architecture
Research Manuscript ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
Work-in-Progress Poster FSMGen: Bridging High-Level Specification and Low-Level Hardware Construction on FPGAs
Research Manuscript Testing, Then Jumping into the Deep (Learning) End
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Research Manuscript Lightning Talk: Processor Vulnerability Discovery
M
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Research Manuscript EENet: Energy Efficient Neural Networks with Run-time Power Management
Research Manuscript OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Research Manuscript RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning
Engineering Track Poster Solving the randomization challenge in CPU verification
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Transformative Technologies Theater Enabling AI at Zettascale: Wafers, Chiplets, or both?
Work-in-Progress Poster SEASONS: Signal and Energy Aware Sensing on iNtermittent Systems
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Work-in-Progress Poster Quickloop: An efficient, FPGA-accelerated exploration of parameterized RTL generators
RISC-V Zone Innovation by Collaboration: CHIPS Alliance
Research Manuscript Breaking the Fault and Yield Barriers
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Work-in-Progress Poster Context-Aware Runtime Model Reconfiguration for Energy-Efficient Autonomous Vehicle Perception
Special Session (Research) Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms
Engineering Track Poster Statistical OCV based Design Closure
Engineering Track Poster Advanced Node PPA and Design Optimization Using Cerebrus ML Flow
Research Manuscript Not Fast Enough? Hardware Acceleration for Transformers and Beyond
Work-in-Progress Poster Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles
Research Panel Sustainable Autonomous Systems Design
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript Faster and stronger Lossless Compression with Optimized Autoregressive framework
Work-in-Progress Poster CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Research Manuscript Ever more optimized simulations of fermionic systems on a quantum computer
Engineering Track Poster Learning Box Model using DSO.ai
Engineering Track Poster Using Machine Learning to Optimize and Accelerate Random Regression Testing
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Research Panel CHIPS & SCIENCE & EDA: A New (and Amplified) Future?
Work-in-Progress Poster SoCurity: A Design Approach for Enhancing SoC Security
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Work-in-Progress Poster An ML based Semi-Static Predictor for Approximate Load Value in Cache Memory
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
DAC Pavilion Panel Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Research Manuscript Leading Developments from the Frontier of High-level Synthesis and Neighborhoods
Work-in-Progress Poster HugFuzz: Human-guided Fuzzing for RTL Designs
Research Manuscript The Path to Reliable, Secure, and Energy-efficient Cloud-edge Continuum
Engineering Track Poster Multi-Policy Lint Signoff for SoCs
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Work-in-Progress Poster Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Gladiator Area Poster Battle A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Work-in-Progress Poster Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Late Breaking Results Poster Late Breaking Results: PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
Work-in-Progress Poster Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Research Manuscript Fantastic AI System Improvements and Where to Find Them
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Front-End Design Design for Verification - Case Reopened
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Work-in-Progress Poster CANCELED - TMD-RAM: Time-Modulated and Data-Aware in-SRAM MAC CMOS Accelerator for CNNs
Gladiator Area Poster Battle Requirement tracing for Design Flow in communication protocols IP
Work-in-Progress Poster Improving Block Management in 3D NAND Flash Memory Using Sub-block First Page Write Sequence
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Work-in-Progress Poster RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Gladiator Area Poster Battle Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Work-in-Progress Poster DAG-aware Synthesis Orchestration
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Research Manuscript This is Formal...But You Can Come Casual!
Engineering Track Poster Addressing Common Verification Pitfalls of Chiplet Interconnects
Research Panel DAC60 Celebration Panel: Designing the Future
Research Panel DAC60 Celebration Panel: Designing the Future
Research Manuscript G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Work-in-Progress Poster APEX: Recommending Design Flow Parameters Using a Variational Autoencoder
Research Manuscript Everything, EveryPLACE, All at Once!
Front-End Design Verification Beyond Coverage
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Late Breaking Results Poster Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly
DAC Pavilion Panel The Industry 4.0 Revolution of Semiconductor Design
Research Manuscript DmTSAR-ILP: Allocating a Unified Domain Platform for Streaming Applications
Front-End Design Formal Verification of Floating-Point Matrix Multiply-Add Designs
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Research Manuscript Global floorplanning via semidefinite programming
Special Session (Research) Will Heterogeneous Integration Drive the Next Phase of Moore's Law?
Engineering Track Poster FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Engineering Track Poster FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Engineering Track Poster Optimal MSCTS Driver duplication for improved H-Tree Clock Skew and Insertion delay
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Engineering Track Poster Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
Special Session (Research) Accelerating Genome Analysis via Algorithm-Architecture Co-Design
Research Manuscript Lightning Talk: Memory-Centric Computing
Transformative Technologies Theater The Good, Bad and Cloudy
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Front-End Design Debug Accelerator & Performance Validator
Work-in-Progress Poster L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Work-in-Progress Poster Mining SoC Message Flows with Self-Attention
Gladiator Area Poster Battle A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Special Session (Research) The Design of Next-Generation Cloud Computing Systems
Engineering Track Poster An efficient methodology to verify floating point matrix multiplication
Work-in-Progress Poster CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks
Work-in-Progress Poster Rectification Learning From Hypotheses Refutation and Relevance Classification
Research Manuscript Ever more optimized simulations of fermionic systems on a quantum computer
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Research Manuscript The Crossroad of AI Paradigms: From Neurons to Bits
Engineering Track Poster A novel methodology for EM/IR analysis of Complex LDO/Power gated designs.
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Front-End Design Verification Beyond Coverage
DAC Pavilion Panel The Industry 4.0 Revolution of Semiconductor Design
Engineering Track Poster Chiplet Design and Verification using an Open Standard Markup Language
Late Breaking Results Poster Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure
Research Manuscript Circuit Design Potpourri
Engineering Track Poster Designing optimal SoC architectures for compute-intensive AI workloads
Research Manuscript Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
Research Manuscript Beyond Moore is Cool
Research Manuscript TD-Magic: From Pictures of Timing Diagrams to Formal Specifications
Research Manuscript Beyond Moore is Cool
Research Manuscript Lightning Talk - In-Memory Computing for AI and ML — A Cross-Layer Perspective
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript SimLL: Similarity-Based Logic Locking against Machine Learning Attacks
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Hands-On Training Session Increase throughput and productivity with Cadence tools in the cloud using flexible AWS compute choices
Back-End Design Over-Design Methodology for Operating Voltage Minimization
Work-in-Progress Poster RODOS: Robust Design Optimization with Simulator Learning
Research Manuscript Got An Acronym? Building Secure Architectures and Accelerators
Engineering Track Poster Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Research Manuscript Novel Techniques in Synthesis and Verification of Analog Circuits
Engineering Track Poster A verification plan to assess the quality of mobile telephony in Brazil
Work-in-Progress Poster How connection delay can affect synchronization with two-factor tools
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Transformative Technologies Theater Intel PowerVia design considerations to optimize SOC design
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Research Manuscript RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning
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Gladiator Area Poster Battle Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis
Engineering Track Poster Design Verification Waveform Analysis through Machine Learning Solution
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Engineering Track Poster Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Research Manuscript Chiplets: How Small is too Small?
Engineering Track Poster MathLib - Math functions Library for SystemVerilog/UVM
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Research Manuscript Infusing Intelligence into Embedded Software
Research Manuscript Circuit Design Potpourri
Late Breaking Results Poster Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Engineering Track Poster PHY Verification IP
Special Session (Research) Algorithms, Architecture, Circuits, and Devices for Genome Sequencing Acceleration
Research Manuscript STT-RAM: STacked, Transactional, and ReconfigurAble Memories
Research Manuscript TCSNN: Time-Conditional Spiking Neural Networks for Efficient In-Memory Computing
Research Manuscript When Bio-inspired Models Met Hardware Optimization
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Research Manuscript Layout Decomposition via Boolean Satisfiability
Late Breaking Results Poster Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Engineering Track Poster CANCELED - Auto-Detection and Unraveling the reasons for the Unoptimized Nets
Special Session (Research) The Algorithms and the need for novel Architectures and Acceleration for Genome Sequence Analysis
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Work-in-Progress Poster A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
Work-in-Progress Poster Fornax: Lightweight Energy-Efficient DNN Accelerator Architecture for Edge Devices
Work-in-Progress Poster Machine learning based design methodology for power optimization of wide range SRAM
Work-in-Progress Poster Wear Leveling of Processing Elements Array in Deep Neural Network Accelerators
Research Manuscript Towards Wider Adoption of Near-Data Processing
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Work-in-Progress Poster High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics
Work-in-Progress Poster A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Engineering Track Poster Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Engineering Track Poster Learning Box Model using DSO.ai
Research Manuscript Greetings from Hardware-friendly AI Algorithms
Engineering Track Poster Rethinking the Usage of Self-Contained Reusable Components
Engineering Track Poster PHY Verification IP
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Work-in-Progress Poster Demands for Open-Source Hardware Trojan Detection Tools: An RL Approach
Transformative Technologies Theater Achieving “System-Driven PPA” on Multi-Chiplet Designs Through Systemic Innovation
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Engineering Track Poster Clustering of Assertions using ML/AI in Formal Verification
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
Transformative Technologies Theater Digital Transformation Platform for Electronics Hardware
Research Manuscript Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
Work-in-Progress Poster CTScan: A CGRA-based Platform for Emulation of Power Side-Channel Attacks on CPUs
Work-in-Progress Poster Secure Run-Time Hardware Trojan Detection using Lightweight Analytical Models
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Work-in-Progress Poster A Computation Interleaving Countermeasure against Profiled Side Channel Attacks
Research Manuscript PROPHET: Predictive On-Chip Power Meter for Hardware DNN Accelerator
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Embedded Systems and Software Edge - AI and Security
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Engineering Track Poster Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
Work-in-Progress Poster A Computation Interleaving Countermeasure against Profiled Side Channel Attacks
Additional Meeting CANCELLED: Designing for Automotive Functional Safety (FuSa) Requirements
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Late Breaking Results Poster Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Front-End Design Dragging Debug into a New Era
Gladiator Area Poster Battle High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
Engineering Track Poster Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Work-in-Progress Poster CuKnit: Optimized Partitioning of Quantum Circuits using Knitting and Cutting
Front-End Design Formal Verification of Floating-Point Matrix Multiply-Add Designs
Work-in-Progress Poster IAM: A Protocol to Improve Security in ISO 15118-20 EV Charging via Remote Attestation
Engineering Track Poster Statistical OCV based Design Closure
Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Engineering Track Poster A Statistical approach to identify wasted power consumption in combinational clusters
Late Breaking Results Poster Late Breaking Results: PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
Engineering Track Poster Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Engineering Track Poster RISC-V processor customization: How to enable heterogeneous compute.
Front-End Design Re-targetable C/C++ LLVM Compiler for RISC-V
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Work-in-Progress Poster Node-level Dynamic Distributed Trust Metric Evaluation
Special Session (Research) Automated Code generation for Information Technology Tasks in YAML through Large Language Models
Engineering Track Poster Learning Box Model using DSO.ai
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Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Work-in-Progress Poster An Efficient Split Fine-tuning Framework for Edge and Cloud Collaborative Learning
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Work-in-Progress Poster MicroNAS: Zero-shot Neural Architecture Search for MCUs
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Work-in-Progress Poster CANCELED - Interleaving-Mapping: A Novel Data Layout in SPRAM
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Research Panel Lost in Silicon: The Need for Re-Innovating the Future of Trusted Hardware and Supply Chain Resilience
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript Lightning Talk - Creative Design Beyond Moore's Law
Research Manuscript Compiler Optimization for Quantum Computing Using Reinforcement Learning
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Research Panel DAC60 Celebration Panel: Designing the Future
Research Panel Is Deep Learning Computationally Sustainable?
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Research Manuscript Discerning the Limitations of GNN-based Attacks on Logic Locking
Engineering Track Poster Accelerating Datapath Verification using Formal techniques
Engineering Track Poster Solving the randomization challenge in CPU verification
Research Manuscript AI a Goldmine for Attackers
Engineering Track Poster SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Engineering Track Poster Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
Engineering Track Poster FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Engineering Track Poster Efficient way of Migration & Comparison of Custom IC Schematic Designs
Engineering Track Poster A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Engineering Track Poster Statistical IR Analysis with Ansys SigmaDvD
Research Manuscript ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Engineering Track Poster Clustering of Assertions using ML/AI in Formal Verification
Engineering Track Poster Special Bit Pattern Injection in Simulation Verification by leveraging Formal Verification
Research Manuscript EP-ORAM: Efficient NVM-Friendly Path Eviction for Ring ORAM in Hybrid Memory
Research Manuscript UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
Engineering Track Poster Clustering of Assertions using ML/AI in Formal Verification
Engineering Track Poster Special Bit Pattern Injection in Simulation Verification by leveraging Formal Verification
Work-in-Progress Poster Improving Block Management in 3D NAND Flash Memory Using Sub-block First Page Write Sequence
Gladiator Area Poster Battle HW Security Path Validation Using Formal Methods: Intel Case Studies
Special Session (Research) Verification of Aerospace Safety Critical Systems: Challenges and Opportunities for Accelerators
Transformative Technologies Theater Tropos Platform - A Novel DevSecOps Platform for IC/FPGA Design
Work-in-Progress Poster CANCELED - TMD-RAM: Time-Modulated and Data-Aware in-SRAM MAC CMOS Accelerator for CNNs
Engineering Track Poster Designing High Performance IC Packages Ensuring Reliability and Cost
Engineering Track Poster Aggressor Aware Design for Better IRdrop Results
Research Manuscript GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs
Late Breaking Results Poster Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Engineering Track Poster Best Practices for Static SignOff
Work-in-Progress Poster CANCELED - A Processing Element for Sparse Tensor Accelerators
Research Manuscript Adventures in Heterogeneous Computing Systems
Research Manuscript Don’t Cross Me! Cross-layer System Security
DAC Pavilion Panel Ask Me Anything with Joe Costello and Wally Rhines
Front-End Design Dragging Debug into a New Era
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Research Manuscript An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript Lightning Talk: Private and Secure Edge AI with Hyperdimensional Computing
Front-End Design Dragging Debug into a New Era
Work-in-Progress Poster From static analyses to runtime verification of cyber-physical systems
Transformative Technologies Theater Accelerate HPC/EDA Outcomes with an All-Inclusive and Efficient Data Life Cycle Management Plan
Engineering Track Poster CANCELED - Early IR Drop Prediction using Machine Learning for Power Grid
Engineering Track Poster EM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs
Research Manuscript Lightning Talk - A Perspective on Neuromorphic Computing
Research Manuscript Let's Network with Chiplets
Work-in-Progress Poster Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles
Research Panel Why is Curvy Design an Opportunity Now?
Research Panel CHIPS & SCIENCE & EDA: A New (and Amplified) Future?
Work-in-Progress Poster Countering the Path Explosion Problem in the Symbolic Execution of Hardware Designs
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Front-End Design Advanced Verification and Debug
Front-End Design Static and Formal
Engineering Track Poster Is your structural CDC sign-off complete?
Engineering Track Poster Multi-Policy Lint Signoff for SoCs
Gladiator Area Poster Battle High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
Research Manuscript BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-parallel Modular Multiplication
Research Manuscript Dear Accelerator, Could You Please Be More Specific?
Research Manuscript Hybrid Obfuscation of Chiplet-Based Systems
Engineering Track Poster Rethinking the Usage of Self-Contained Reusable Components
Work-in-Progress Poster Arrow: A Soft RISC-V Vector Accelerator for Machine Learning Inference
Engineering Track Poster Deep learning Platform for FSM-Based HLS
Work-in-Progress Poster Applying Graph Explanation to Operator Fusion
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Research Manuscript Design for Manufacturing: Make It or Break It
Engineering Track Poster Using Machine Learning to Optimize and Accelerate Random Regression Testing
Research Panel DAC60 Celebration Panel: Designing the Future
Engineering Track Poster Design Verification Waveform Analysis through Machine Learning Solution
Work-in-Progress Poster Zero Trust Verification of Third Party IPs with Secure Multiparty Computing
Engineering Track Poster SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Work-in-Progress Poster Demands for Open-Source Hardware Trojan Detection Tools: An RL Approach
Research Manuscript Do You Know What You Will Get from Lithography?
Work-in-Progress Poster NoNL-DFR: New Model of Digital Delayed Feedback Reservoir without Nonlinear Elements
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript Lightning Talk - The Incredible Shrinking Black Box Model
Special Session (Research) Pre-silicon physical Security Verification: Finding Haystack Needles before They Sting
Research Manuscript DmTSAR-ILP: Allocating a Unified Domain Platform for Streaming Applications
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Research Manuscript Hybrid Obfuscation of Chiplet-Based Systems
Engineering Track Poster Advanced Node PPA and Design Optimization Using Cerebrus ML Flow
Transformative Technologies Theater Hybrid Cloud Bursting In Enterprises
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Work-in-Progress Poster A Discrete 2.5D Chiplet Library and Optimized Mapping of AI Algorithms for Heterogeneous In-memory Acceleration
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Engineering Track Poster Learning Box Model using DSO.ai
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Engineering Track Poster 3DIC Design floorplanning flow and Early Area Estimation for Area optimization
Late Breaking Results Poster Late Breaking Results: From Hybrid Design Automation for Field-coupled Nanotechnologies
Engineering Track Poster Credit Based scheduling for Precision time protocol frames in Automotive Ethernet
Engineering Track Poster Credit Based scheduling for Precision time protocol frames in Automotive Ethernet.
Additional Meeting Uncovering Blind Spots: Reliability Monitoring of Chiplet-Based Designs
Work-in-Progress Poster CANCELED - TMD-RAM: Time-Modulated and Data-Aware in-SRAM MAC CMOS Accelerator for CNNs
Engineering Track Poster Advanced transceiver components for robust handling of signal noise and loss
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Work-in-Progress Poster Graph Machine Learning assisted Analog Circuit Designing
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Work-in-Progress Poster CANCELED - TMD-RAM: Time-Modulated and Data-Aware in-SRAM MAC CMOS Accelerator for CNNs
Transformative Technologies Theater Intel PowerVia design considerations to optimize SOC design
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Research Manuscript Eficient ILT via Multi-level Lithography Simulation
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Embedded Systems and Software Defining Avionics System Architecture For Multiple Use Cases With Stringent Requirements Using System Modelling
Engineering Track Poster Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Front-End Design Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Research Manuscript Accelerating DNN Inference with Heterogeneous Multi-DPU Engines
Research Manuscript Learning with Drives and Convertibles - from Near Data to Cloud
Engineering Track Poster Aggressor Aware Design for Better IRdrop Results
Engineering Track Poster Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
Gladiator Area Poster Battle A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Research Manuscript Novel Techniques in Synthesis and Verification of Analog Circuits
Special Session (Research) Compute Express Link (CXL*): Open Interconnect for Cloud Infrastructure
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Engineering Track Poster Is your structural CDC sign-off complete?
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Embedded Systems and Software Designing Effective Autonomous Systems and Digital Twins
Work-in-Progress Poster Accurate and Fast Method to Close Design vs Silicon Gap
Research Manuscript EENet: Energy Efficient Neural Networks with Run-time Power Management
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Research Manuscript Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
Research Manuscript On-Device Unsupervised Image Segmentation
Research Manuscript ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks
Work-in-Progress Poster Efficient Accelerator Integration with Generated Modules
Work-in-Progress Poster FuseDM: Accelerating Diffusion Model Sampling on Versal ACAP Architecture
Principal, Research Analyst
Additional Meeting What the Next Semiconductor Upcycle Will Look Like for EDA
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Work-in-Progress Poster An Efficient Split Fine-tuning Framework for Edge and Cloud Collaborative Learning
Research Manuscript Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Research Manuscript AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Work-in-Progress Poster DeepSeq: Deep Sequential Circuit Learning
Research Manuscript On EDA-Driven Learning for SAT Solving
Research Manuscript Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Work-in-Progress Poster ProHash: A Promotion-based Hashing Index Scheme for NVM-based Systems
Engineering Track Poster Automated Design-aware optimized Fill Methodology
Research Manuscript AVX Timing Side-Channel Attacks against Address Space Layout Randomization*
Research Manuscript Investigating Data for DNN Acceleration!
Research Manuscript Lightning Talk - EDA with ML, Rule-Based, or Both?
Research Panel Where Will AI Change EDA: Inside, Outside or Not At All?
Gladiator Area Poster Battle Static Analysis for Early Detection and Efficient Debug
Research Manuscript Everything, EveryPLACE, All at Once!
Work-in-Progress Poster HugFuzz: Human-guided Fuzzing for RTL Designs
Additional Meeting CANCELLED: Designing for Automotive Functional Safety (FuSa) Requirements
Late Breaking Results Poster Late Breaking Results: PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
Gladiator Area Poster Battle A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Research Panel Sustainable Autonomous Systems Design
Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Gladiator Area Poster Battle Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Engineering Track Poster Designing optimal SoC architectures for compute-intensive AI workloads
Engineering Track Poster IO Designs for reliability in advanced technology nodes
Gladiator Area Poster Battle Automated Clock Analysis, Skew Group Generation & CT Verification
Engineering Track Poster A Method to Plan & Generate IO Ring based on CSV Specifications
Front-End Design Low power DAC sub-system for Digital Beam Forming Chip
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Work-in-Progress Poster FPGA Implementation of Efficient 2D-FFT Beamforming for On-Board Processing in Satellites
Engineering Track Poster Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Transformative Technologies Theater Hybrid Cloud Bursting In Enterprises
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Hands-On Training Session Build a Cadence Burst-to-Cloud workflow with NetApp “Design Anywhere” on AWS
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Research Manuscript Fast Adversarial Training with Dynamic Batch-level Attack Control
Research Manuscript Critical Paths Prediction Under Multiple Corners Based on BiLSTM Network
Research Manuscript Occamy: Memory-efficient GPU Compiler for DNN Inference
Work-in-Progress Poster Fornax: Lightweight Energy-Efficient DNN Accelerator Architecture for Edge Devices
Work-in-Progress Poster Wear Leveling of Processing Elements Array in Deep Neural Network Accelerators
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Engineering Track Poster FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
Research Manuscript Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment
RISC-V Zone Why RISC-V is Inevitable
RISC-V Zone Why RISC-V is inevitable
DAC Pavilion Panel Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Additional Meeting CANCELLED: Designing for Automotive Functional Safety (FuSa) Requirements
Research Manuscript Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Work-in-Progress Poster Real-time Deep Visual Tracking on a Tight Budget
Engineering Track Poster MathLib - Math functions Library for SystemVerilog/UVM
Engineering Track Poster Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Engineering Track Poster An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Engineering Track Poster An efficient methodology to verify floating point matrix multiplication
Engineering Track Poster Using Machine Learning to Optimize and Accelerate Random Regression Testing
Research Manuscript Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Transformative Technologies Theater The Good, Bad and Cloudy
Back-End Design System Power Integrity Analysis: from the PMIC to the Transistor
Engineering Track Poster CANCELED - Deriving Optimal Unique Multi Instances In Large SoCs
Engineering Track Poster CANCELED - Deriving Optimal Unique Multi Instances In Large SoCs
Engineering Track Poster Statistical IR Analysis with Ansys SigmaDvD
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Work-in-Progress Poster Novel Adaptive Quantization Methodology for 8-bit Floating-Point DNN Training
Work-in-Progress Poster HugFuzz: Human-guided Fuzzing for RTL Designs
Engineering Track Poster SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Work-in-Progress Poster CANCELED - Towards Large-Scale Routing: A Novel Learning Based Divide & Merge Approach
Research Manuscript New Waves of Boosting Power Efficiency
Work-in-Progress Poster Energy-efficient Personalized Federated Search with Graph for Edge Computing
Research Manuscript Eficient ILT via Multi-level Lithography Simulation
Research Manuscript Optimal Synthesis of Multi-Controlled Qudit Gates
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Research Manuscript All Routes to Timing Closure
Research Manuscript R-TOSS: A Framework for Real-Time Object Detection using Semi-Structured Pruning
Front-End Design Design for Verification - Case Reopened
Work-in-Progress Poster Graph Machine Learning assisted Analog Circuit Designing
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Front-End Design Design for Verification - Case Reopened
Work-in-Progress Poster An ML based Semi-Static Predictor for Approximate Load Value in Cache Memory
Engineering Track Poster Designing High Performance IC Packages Ensuring Reliability and Cost
Transformative Technologies Theater Unleashing Semiconductor Innovation by Fostering Resilient Ecosystems
Research Manuscript Design for Manufacturing: Make It or Break It
Research Manuscript ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Work-in-Progress Poster IAM: A Protocol to Improve Security in ISO 15118-20 EV Charging via Remote Attestation
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Research Manuscript Unleashing Privacy for AI
Research Manuscript Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript Making AI Smarter, Faster, and More Efficient
Research Manuscript EP-ORAM: Efficient NVM-Friendly Path Eviction for Ring ORAM in Hybrid Memory
Research Manuscript Reaction Time Analysis of Event-Triggered Processing Chains with Data Refreshing
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Work-in-Progress Poster CTScan: A CGRA-based Platform for Emulation of Power Side-Channel Attacks on CPUs
Engineering Track Poster A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Research Panel Why is Curvy Design an Opportunity Now?
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Research Manuscript Progress from the Leading Edge of RTL Synthesis
Engineering Track Poster Electrical Analysis using Hierarchical Approach On Ultra Large Designs
Engineering Track Poster Advanced transceiver components for robust handling of signal noise and loss
Research Manuscript UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
Research Manuscript Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Engineering Track Poster IO Designs for reliability in advanced technology nodes
Work-in-Progress Poster IAM: A Protocol to Improve Security in ISO 15118-20 EV Charging via Remote Attestation
Engineering Track Poster RV (Reliability Verification) Automation To Improve Execution Efficiency
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Late Breaking Results Poster Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Late Breaking Results Poster Late Breaking Results: PyAIE: A Python-based Programming Framework for Versal ACAP Platforms
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Special Session (Research) Robust Runtime Systems for Superconducting and Neutral Atom Based Noisy Quantum Hardware
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Work-in-Progress Poster unSAFE: Cunning Sensor Attack via Firmware Reverse-Engineering
Research Manuscript Rethinking Programming Frameworks for In-Storage Processing
Late Breaking Results Poster Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Late Breaking Results Poster Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript AutoDCIM: An Automated Digital CIM Compiler
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Transformative Technologies Theater Chip Design - Cloud & Efficiency
Research Manuscript Lightning Talk: Feasibility Checking for Advanced Packaging
Transformative Technologies Theater The Good, Bad and Cloudy
Engineering Track Poster An efficient methodology to verify floating point matrix multiplication
Front-End Design Crossing the RISC-V customization barrier with formal
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Engineering Track Poster 3D IC Inter-Die Test Implementation Using IEEE1838
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Engineering Track Poster MathLib - Math functions Library for SystemVerilog/UVM
Gladiator Area Poster Battle Automated Clock Analysis, Skew Group Generation & CT Verification
Engineering Track Poster Packet Processing Scaling a flexible scalable approach
Back-End Design Packaging and Manufacturing Technologies save the day!
Back-End Design Packaging and Manufacturing Technologies save the day!
Embedded Systems and Software AUTOSAR Classic Platform Demonstrator
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Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Research Manuscript Hybrid Obfuscation of Chiplet-Based Systems
Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Special Session (Research) Gone in 60M seconds: Challenges for Presilicon SCA and FI simulations
Research Manuscript HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
Research Manuscript Power Side-Channel Vulnerability Assessment of LightWeight Cryptographic Scheme, XOODYAK
Special Session (Research) Pre-Silicon security assurance for SCA and FI: an industry perspective
Gladiator Area Poster Battle Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Transformative Technologies Theater Maximize designer productivity through Microsoft's new cloud native, on-demand, secure collaborative design environment
Engineering Track Poster SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Engineering Track Poster MathLib - Math functions Library for SystemVerilog/UVM
Research Manuscript Efficient Transformer Inference with Statically Structured Sparse Attention
Transformative Technologies Theater Are We There Yet? From Cloud-compatible to Cloud-optimized
Engineering Track Poster Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY
Engineering Track Poster Intent Based Timing Constraints
Work-in-Progress Poster L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Engineering Track Poster Schematic aware IP Compiler : Improving Productivity with Relative Placement
Engineering Track Poster Efficient methodologies for STL certification of Spinoff SOC designs.
Engineering Track Poster Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Analyst Presentation A View from Wall Street: The State of EDA
DAC Pavilion Panel Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
Engineering Track Poster SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
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Engineering Track Poster Layout Proximity Effect On Interconnect Capacitance
Work-in-Progress Poster CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Late Breaking Results Poster Late Breaking Results: From Hybrid Design Automation for Field-coupled Nanotechnologies
Work-in-Progress Poster Move-On-Cover: An Efficient Secure Deletion Strategy for Interlaced Magnetic Recording
Work-in-Progress Poster Efficient Pareto Point Propagation Algorithm for HLS Design Space Exploration
Research Manuscript Expanding Compute-in-Memory for Emerging Machine Learning
Embedded Systems and Software Edge - AI and Security
Embedded Systems and Software Edge - AI and Security
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript Global floorplanning via semidefinite programming
Research Manuscript Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Work-in-Progress Poster A cost-generic logic synthesis framework with customizable cost functions
Work-in-Progress Poster A RISC-V Instruction Level Acceleration for FFT
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript A Comprehensive Automated Exploration Framework for Systolic Array Designs
Research Manuscript IP Protection in Tiny ML
Research Manuscript DistHD: A Learner-Aware Encoding Method for Hyperdimensional Classification
Late Breaking Results Poster Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection
Work-in-Progress Poster AMACC: Asynchronous Memory Access Accelerator for RISC-V Embedded Soft Processors
Engineering Track Poster Integration of Intel Thermal Model with Design-for-Reliability Flow
Research Manuscript Ever more optimized simulations of fermionic systems on a quantum computer
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Work-in-Progress Poster MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
Work-in-Progress Poster AMACC: Asynchronous Memory Access Accelerator for RISC-V Embedded Soft Processors
Work-in-Progress Poster VSAGE: an End-to-End Automated VCO-based ΔΣ ADC Generator
Special Session (Research) Toward Provably Correct Hardware Accelerator Design: Perspectives, Opportunities, and Challenges
Research Manuscript Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
Engineering Track Poster Power Integrity analysis of 3D stacking Structure in CMOS Image Sensor Chip
Research Manuscript ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
Late Breaking Results Poster Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Work-in-Progress Poster An Efficient Split Fine-tuning Framework for Edge and Cloud Collaborative Learning
Research Manuscript Efficient AI for the Edge: From Head to Toe!
Special Session (Research) Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration
Research Manuscript Condense: A Framework for Device and Frequency Adaptive Neural Network Models on the Edge
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Research Manuscript DriverJar: Lightweight Device Driver Isolation for ARM
Research Manuscript APPEND: Towards Application Enhanced NPU Designing
Research Manuscript AmgR: Algebraic Multigrid Accelerated on ReRAM
Research Manuscript Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Research Manuscript An Efficient Accelerator for Point-based and Voxel-based Point Cloud Neural Networks
Research Manuscript Memory-Efficient and Real-Time SPAD-based dToF Imaging with Spatial and Statistical Correlation
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Special Session (Research) Cloud and Edge: New Age of Automotive Computing
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Analyst Presentation The AI Hardware Show Live: Silicon or Survival
Transformative Technologies Theater Alternative approaches to AI chip architectures
Transformative Technologies Theater Enabling AI at Zettascale: Wafers, Chiplets, or both?
Special Session (Research) Machine Learning Sensors: Building Blocks for AI-enabled Systems
Transformative Technologies Theater Have your cake and eat it: Reliably running stateful virtual machines in cheap spot markets.
Engineering Track Poster High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Work-in-Progress Poster Novel Adaptive Quantization Methodology for 8-bit Floating-Point DNN Training
Research Manuscript Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Embedded Systems and Software Early Android Software Verification With RISC-V Virtual Platforms
Work-in-Progress Poster SoCurity: A Design Approach for Enhancing SoC Security
Research Manuscript Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Work-in-Progress Poster LUNAR: A Native Table Engine for IoT Devices
Research Manuscript HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Research Manuscript An Odyssey in Quantum Circuits: Unleashing the Power of Quantum Computing
Work-in-Progress Poster CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Research Manuscript Compiler Optimization for Quantum Computing Using Reinforcement Learning
Research Manuscript Design Automation for Cryogenic CMOS Circuits
Late Breaking Results Poster Late Breaking Results: From Hybrid Design Automation for Field-coupled Nanotechnologies
Engineering Track Poster Chiplet Design and Verification using an Open Standard Markup Language
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Research Manuscript On a Moreau Envelope Wirelength Model for Analytical Global Placement
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Work-in-Progress Poster CANCELED - A Unifying Tensor View for Lightweight CNNs
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Research Manuscript BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing
Work-in-Progress Poster Efficient Pareto Point Propagation Algorithm for HLS Design Space Exploration
Research Manuscript Condense: A Framework for Device and Frequency Adaptive Neural Network Models on the Edge
Research Manuscript RLAlloc: A Deep Reinforcement Learning-Assisted Resource Allocation Framework for Enhanced Both I/O Throughput and QoS Performance of Multi-Streamed SSDs
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript A digital 3D TCAM accelerator for the inference phase of Random Forest
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Transformative Technologies Theater Chip Design - Cloud & Efficiency
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Research Manuscript DriverJar: Lightweight Device Driver Isolation for ARM
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Work-in-Progress Poster Real-time Deep Visual Tracking on a Tight Budget
Work-in-Progress Poster MALICE: Manipulation Attacks on Learned Image ComprEssion
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript IP Protection in Tiny ML
Transformative Technologies Theater Enabling AI at Zettascale: Wafers, Chiplets, or both?
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Work-in-Progress Poster An Efficient Split Fine-tuning Framework for Edge and Cloud Collaborative Learning
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Work-in-Progress Poster FSMGen: Bridging High-Level Specification and Low-Level Hardware Construction on FPGAs
Research Manuscript Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Special Session (Research) TinyML: Bring Deep Learning Models to Tiny Devices
Work-in-Progress Poster VSAGE: an End-to-End Automated VCO-based ΔΣ ADC Generator
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript PROPHET: Predictive On-Chip Power Meter for Hardware DNN Accelerator
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Engineering Track Poster Advanced transceiver components for robust handling of signal noise and loss
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Research Manuscript Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Research Manuscript Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Work-in-Progress Poster MicroNAS: Zero-shot Neural Architecture Search for MCUs
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Work-in-Progress Poster DeepSeq: Deep Sequential Circuit Learning
Research Manuscript On EDA-Driven Learning for SAT Solving
Research Manuscript Improving Standard-Cell Design Flow using Factored Form Optimization
Research Manuscript Faster and stronger Lossless Compression with Optimized Autoregressive framework
Research Manuscript STT-RAM: STacked, Transactional, and ReconfigurAble Memories
Work-in-Progress Poster Cluster-based hierarchical HLS design optimization
Research Manuscript Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment
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Engineering Track Poster A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Gladiator Area Poster Battle Automated Clock Analysis, Skew Group Generation & CT Verification
Engineering Track Poster Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Gladiator Area Poster Battle Static Analysis for Early Detection and Efficient Debug
Engineering Track Poster Power Integrity analysis of 3D stacking Structure in CMOS Image Sensor Chip
Work-in-Progress Poster LUNAR: A Native Table Engine for IoT Devices
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Work-in-Progress Poster Qubit Mapping Toward Quantum Advantage
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Research Manuscript Eficient ILT via Multi-level Lithography Simulation
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Work-in-Progress Poster Analog System High-level Synthesis to Physical Devices
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Research Manuscript ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
Research Manuscript Memory-Efficient and Real-Time SPAD-based dToF Imaging with Spatial and Statistical Correlation
Research Manuscript PIM-HLS: Automatic Hardware Generation and Scheduling for Processing-in-Memory-based Neural Network Accelerators
Late Breaking Results Poster Late Breaking Results: PVT-Sensitive Delay Fitting for High Performance Computing
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Special Session (Research) A Scalable Formal Approach for Correctness-Assured Hardware Design
Research Manuscript Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
Front-End Design Emulation Based Automation Platform For SoC Performance Verification
Research Manuscript Investigating Data for DNN Acceleration!
Late Breaking Results Poster Late Breaking Results: PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Late Breaking Results Poster Late Breaking Results: RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network
Research Manuscript EP-ORAM: Efficient NVM-Friendly Path Eviction for Ring ORAM in Hybrid Memory
Research Manuscript Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
Research Manuscript On-Device Unsupervised Image Segmentation
Work-in-Progress Poster CANCELED - SecGraph: Security Oriented Graph NeuRal Network Assisted Protection on Hardware
Research Manuscript SimLL: Similarity-Based Logic Locking against Machine Learning Attacks
Work-in-Progress Poster Move-On-Cover: An Efficient Secure Deletion Strategy for Interlaced Magnetic Recording
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Research Manuscript Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
Research Manuscript On-Device Unsupervised Image Segmentation
Work-in-Progress Poster Analog System High-level Synthesis to Physical Devices
Work-in-Progress Poster CANCELED - Towards Large-Scale Routing: A Novel Learning Based Divide & Merge Approach
Work-in-Progress Poster An Efficient Split Fine-tuning Framework for Edge and Cloud Collaborative Learning
Late Breaking Results Poster Late Breaking Results: PyAIE: A Python-based Programming Framework for Versal ACAP Platforms
Research Manuscript HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Work-in-Progress Poster Energy-efficient Personalized Federated Search with Graph for Edge Computing
Research Manuscript Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
Research Manuscript "ML under Attack, and ML for Attacks and Defenses"
Engineering Track Poster Camelus: Scalable and Generic SIMD Programming for AI Accelerators
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript Pathfinding Model and Lagrangian-Based Global Routing
Work-in-Progress Poster Fuzzing and Static Analysis Guided Symbolic Execution to Detect Hardware Trojans
Work-in-Progress Poster GEBA: Gradient-Error-Based Approximation of Activation Functions
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript Intermittent-Aware Neural Network Pruning
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Gladiator Area Poster Battle Novel Hierarchical IREM Sign-off Flow using ROM
Research Manuscript Graph Representation Learning for Microarchitecture Design Space Exploration
Work-in-Progress Poster AutoSparse: Automatic Search for Efficient Activation Sparsity-aware CNN Accelerator
Work-in-Progress Poster Efficient Transformation of Architectures through Hardware-aware Nonlinear Optimization
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
Work-in-Progress Poster Spike-Predictable Neuron Circuits with Adaptive Threshold for Low-power SNN Systems
Engineering Track Poster Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
Special Session (Research) Codesign from Semiconductors to AI
Research Manuscript EDGE: Efficient DAG-based Global Routing Engine
Research Manuscript Lightning Talk - Design for Manufacturing: Make It or Break It
Research Manuscript Rethinking AIG Resynthesis in Parallel*
Research Panel CHIPS & SCIENCE & EDA: A New (and Amplified) Future?
Engineering Track Poster Efficient way of Migration & Comparison of Custom IC Schematic Designs
Research Manuscript Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Eficient ILT via Multi-level Lithography Simulation
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Research Manuscript On a Moreau Envelope Wirelength Model for Analytical Global Placement
Research Manuscript OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration
Research Manuscript Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Research Manuscript Restructure-Tolerant Timing Prediction via Multimodal Fusion
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Special Session (Research) Autonomous Driving Digital Twin Empowered Design Automation: An Industry Perspective
Work-in-Progress Poster Accelerating Exact Combinatorial Optimization via RL-based Initialization – A Case Study in Scheduling
Research Manuscript Breaking news from RTL technology-independent optimization
Work-in-Progress Poster DAG-aware Synthesis Orchestration
Research Manuscript Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks*
Research Manuscript Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Research Panel DAC60 Celebration Panel: Designing the Future
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Research Manuscript Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints
Research Manuscript PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration
Research Manuscript Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints
Late Breaking Results Poster Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Research Manuscript STCG: State Aware Test Case Generation for Simulink Models
Research Manuscript DSPIMM: Digital Sparse In-Memory matrix vector multplier for Communication Applications.
Research Manuscript IP Protection in Tiny ML
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
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Embedded Systems and Software AI on the Edge! Challenges and solutions for Edge AI products
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Embedded Systems and Software Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Engineering Track Poster Efficient way of Migration & Comparison of Custom IC Schematic Designs
Engineering Track Poster Efficient way of Migration & Comparison of Custom IC Schematic Designs
Research Manuscript Let's Get with the Processing-in-Memory Program
Research Manuscript Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning
Research Manuscript Eficient ILT via Multi-level Lithography Simulation
Research Manuscript FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Work-in-Progress Poster Move-On-Cover: An Efficient Secure Deletion Strategy for Interlaced Magnetic Recording
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Research Manuscript MPass: Bypassing Learning-based Static Malware Detectors
Research Manuscript PTStore: Lightweight Architectural Support for Page Table Isolation
Engineering Track Poster Novel Chip-Package-System thermal analysis with RTL Power
Work-in-Progress Poster Static Program Analysis against Risky IoT Interaction in Zero Knowledge Settings
Research Manuscript Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Research Manuscript AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript The Crossroad of AI Paradigms: From Neurons to Bits
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Work-in-Progress Poster NeuroPDR: Integrating Neural Networks in PDR Algorithm for Hardware Model Checking
Engineering Track Poster A Novel Fitting Method of Package Material Parameters Base On MOP
Research Manuscript DriverJar: Lightweight Device Driver Isolation for ARM
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Work-in-Progress Poster Enabling Efficient NVM-Based Text Analytics without Decompression
Research Manuscript AI a Goldmine for Attackers
Research Manuscript IP Protection in Tiny ML
Research Manuscript New Discoveries in Classical Hardware Security Problems
Research Manuscript Pathfinding Model and Lagrangian-Based Global Routing
Research Manuscript AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Research Manuscript CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Engineering Track Poster Novel Chip-Package-System thermal analysis with RTL Power
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Research Manuscript Contention-Free Configured Grant Scheduling for 5G URLLC Traffic
Work-in-Progress Poster NeuroPDR: Integrating Neural Networks in PDR Algorithm for Hardware Model Checking
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript PROPHET: Predictive On-Chip Power Meter for Hardware DNN Accelerator
Work-in-Progress Poster Context-Aware Runtime Model Reconfiguration for Energy-Efficient Autonomous Vehicle Perception
Research Manuscript FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
Work-in-Progress Poster SuperFlow: A RTL-to-GDS Design Flow for AQFP Superconducting Devices
Work-in-Progress Poster Context-Aware Runtime Model Reconfiguration for Energy-Efficient Autonomous Vehicle Perception
Work-in-Progress Poster MicroNAS: Zero-shot Neural Architecture Search for MCUs
Work-in-Progress Poster CANCELED - Multi-objective optimization for Floating Point Mix-Precision Tuning
Research Manuscript EP-ORAM: Efficient NVM-Friendly Path Eviction for Ring ORAM in Hybrid Memory
Research Manuscript LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Research Manuscript $\mathbf{C^2PI}$: Crypto-Clear Private Inference
Research Manuscript On-Device Unsupervised Image Segmentation
Engineering Track Poster The Benefits of Formal Signoff on New and Mature Designs
Research Manuscript DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
Research Manuscript Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
Research Manuscript General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Work-in-Progress Poster Shift-SRAM: A Novel Architecture For Accelerating MAC Operation By Leveraging Bit-Wise Sparsity
Research Manuscript ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Research Manuscript PSMiner: A Pattern-Aware Accelerator for High-Performance Streaming Graph Pattern Mining
Research Manuscript SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
Work-in-Progress Poster ReARVR: A ReRAM-based DNN accelerator for mobile AR/VR devices
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Research Manuscript Reinforcement Learning-Assisted Management for Convertible SSDs
Work-in-Progress Poster Neuromorphic System-on-Chip Towards Efficient Edge Healthcare
Research Manuscript Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms
Research Manuscript TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
Research Manuscript DiffPattern: Layout Pattern Generation via Discrete Diffusion
Research Manuscript Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Work-in-Progress Poster A High-Performance Accelerator for Online Symbolic Regression
Research Manuscript A Farewell to the Numerical Computing Paradigm
Research Manuscript Making AI Smarter, Faster, and More Efficient
Work-in-Progress Poster Mining SoC Message Flows with Self-Attention
Research Manuscript Correlation-guided Placement for Nonvolatile FPGAs
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript PRIMER: A Privacy-Preserving Transformer on Encrypted Data
Work-in-Progress Poster MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
China
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Work-in-Progress Poster GCN-based Floorplanning with Dirichlet Boundary Conditions
Engineering Track Poster Camelus: Scalable and Generic SIMD Programming for AI Accelerators
Work-in-Progress Poster CANCELED - A Unifying Tensor View for Lightweight CNNs
Work-in-Progress Poster DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Special Session (Research) Design the Clouds: Acceleration, Interconnect, and Infrastructure
Research Manuscript High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives
Research Manuscript NASA in DAC?
Work-in-Progress Poster UnrealNAS: do neural architecture search with no labels
Transformative Technologies Theater Chip Design - Cloud & Efficiency
Research Manuscript DriverJar: Lightweight Device Driver Isolation for ARM
Research Manuscript MeG2: In-Memory Acceleration for Genome Graphs Analysis
Research Manuscript Efficient AI for the Edge: From Head to Toe!
Work-in-Progress Poster Static Program Analysis against Risky IoT Interaction in Zero Knowledge Settings
Research Manuscript Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Research Manuscript Fast but Not Precarious: Meeting Efficiency Challenges in Autonomous Systems
Special Session (Research) Waving the Double-Edged Sword: Building Resilient CAVs with Edge and Cloud Computing
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Research Manuscript Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Research Manuscript Pathfinding Model and Lagrangian-Based Global Routing
Research Manuscript A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Research Manuscript Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Research Manuscript BLITZCRANK: Factor Graph Accelerator for Motion Planning
Work-in-Progress Poster EPIM: Efficient Processing-In Memory Accelerators based on Epitome
Research Manuscript Memory-Efficient and Real-Time SPAD-based dToF Imaging with Spatial and Statistical Correlation
Research Manuscript DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Research Manuscript Optimal Synthesis of Multi-Controlled Qudit Gates
Research Manuscript Lightweight Structural Choices Operator for Technology Mapping
Research Manuscript EENet: Energy Efficient Neural Networks with Run-time Power Management
Research Manuscript Mitigating Distribution Shift for Congestion Optimization in Global Placement
Engineering Track Poster A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Research Manuscript Layout Decomposition via Boolean Satisfiability
Research Manuscript A High-accurate Multi-objective Exploration Framework for Design Space of CPU
Work-in-Progress Poster A RISC-V Instruction Level Acceleration for FFT
Work-in-Progress Poster Comprehensive Analysis of Hyperdimensional Computing against Gradient-Based Attacks
Research Manuscript RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning