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Organization

Peking University
Presenters
Renze Chen
Siyuan Chen
Yifan Chen
Yiyang Chen
Tuo Dai
Yanchi Dong
Kaixuan Du
Mingfei Guo
Zizheng Guo
Lixia Han
Yixuan Hu
Peng Huang
Ru Huang
Tianyu Jia
Xun Jiang
Yiqi Jing
Jinfeng Kang
Cong Li
Meng Li
Xingchen Li
Yun Liang
Yibo Lin
Xiaoyan Liu
Guojie Luo
Zizhang Luo
Yufei Ma
Bizhao Shi
Guangyu Sun
Qipan Wang
Runsheng Wang
Yuan Wang
Renjie Wei
Xinming Wei
Xuechao Wei
Zaiwen Wen
Youwei Xiao
Zhonglin Xie
Le Ye
Jiaxi Zhang
Shanghang Zhang
Tengyu Zhang
Zuodong Zhang
Size Zheng
Zhe Zhou
Zheng Zhou
Session Chairs
Yibo Lin
Presentations
Research Manuscript
A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
EDA
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
EDA
Physical Design and Verification
Research Manuscript
CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification
AI
AI/ML Algorithms
Work-in-Progress Poster
Efficient Accelerator Integration with Generated Modules
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network
Design
AI/ML Architecture Design
Work-in-Progress Poster
FSMGen: Bridging High-Level Specification and Low-Level Hardware Construction on FPGAs
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Work-in-Progress Poster
FuseDM: Accelerating Diffusion Model Sampling on Versal ACAP Architecture
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs.
RISC-V
Security
Hardware Security: Attack and Defense
Research Manuscript
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
EDA
Design Verification and Validation
Work-in-Progress Poster
GPP-Map: Graph Neural Network and Polyhedral Model Assisted Parallel CGRA Mapping Optimization Framework
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
EDA
Design for Manufacturing and Reliability
Work-in-Progress Poster
MCUGen: Memory Efficient Mapping and Code Generation for DNN Inference on MCUs
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
Memory and Computation Coordinated Mapping of DNNs onto Complex Heterogeneous SoC
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Mitigating Distribution Shift for Congestion Optimization in Global Placement
EDA
Physical Design and Verification
Research Manuscript
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
On a Moreau Envelope Wirelength Model for Analytical Global Placement
EDA
Physical Design and Verification
Research Manuscript
Rubick: A Synthesis Framework For Spatial Architectures via Dataflow Decomposition
EDA
RTL/Logic Level and High-level Synthesis
Tutorial
Timing Challenges at Advanced Technology Nodes and Acceleration by Heterogeneous Programming and Machine Learning
AI
EDA
Work-in-Progress Poster
UnrealNAS: do neural architecture search with no labels
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Sessions
Research Manuscript
All Routes to Timing Closure
EDA
RISC-V
Timing and Low Power Design