Close
 

Organization

Georgia Institute of Technology
Presenters
Muya Chang
Brian Crafton
Serhat Erdogan
Yonggan Fu
Anupam Golder
Jennifer Halser
Cong "Callie" Hao
Kevin Hutto
Afolabi Ige
Mohanalingam Kathaperumal
Hyesoon Kim
Ashwin Sanjay Lele
Chaojian Li
Ken Li
Shaolan Li
Sixu Li
Sung Kyu Lim
Yingyan (Celine) Lin
Yi-Chen Lu
Vincent Mooney
Saibal Mukhopadhyay
Arijit Raychowdhury
Zhixin Song
Samuel Spetalnick
Blaise Tine
Pruek Vanna-iampikul
Zishen Wan
RenChu Wang
Tzuhan Wang
Shang Wu
Tian Xie
Hang Yang
Linhao Yang
Yingyan (Celine) Yin
Haoran You
Zhongzhi Yu
Jingqun Zhang
Yongan Zhang
Yang Zhao
Lingjun Zhu
Session Chairs
Muhannad Bakir
Cong (Callie) Hao
Yingyan Lin
Saibal Mukhopadhyay
Presentations
Work-in-Progress Poster
Analog System High-level Synthesis to Physical Devices
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Tutorial
AutoDL: Automated Tools for Fast Development of Deep Learning Networks and Accelerators
AI
Research Manuscript
BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems
Autonomous Systems
Cloud
Autonomous Systems (Automotive, Robotics, Drones)
Special Session (Research)
Cross-Layer Innovations for Enabling Real-Time and Efficient Eye Tracking in VR/AR
AI
Special Session (Research)
Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps
EDA
Research Manuscript
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks*
EDA
Design Verification and Validation
Research Manuscript
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Signal/Power Integrity Benefits
Design
AI/ML, Digital, and Analog Circuits
Back-End Design
Hardware and Software Technologies continue to advance, in close collaboration
Back-End Design
Research Manuscript
Hybrid Gate-Pulse Model for Variational Quantum Algorithms
Design
Quantum Computing
Back-End Design
Implementation Challenges in complex 3D/heterogeneous architectures
Back-End Design
Research Manuscript
Instant-NeRF: Instant On-Device Neural Radiance Field Training via Algorithm-Accelerator Co-Designed Near-Memory Processing
Design
AI/ML Architecture Design
Late Breaking Results Poster
Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Lightning Talk - "Making AI Smarter, Faster, and More Efficient": Current Approaches and Looking into the Future
AI
AI/ML Algorithms
Research Manuscript
Lightning Talk: High Fidelity Benchmarking of Interposer Material Choices Using 2.5D Design Tools
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
NetBooster: Empowering Tiny Deep Learning By Standing on the Shoulders of Deep Giants
AI
AI/ML Algorithms
Research Manuscript
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for solving QUBO Problem
Design
Emerging Models of Computation
Research Manuscript
Power Side-Channel Vulnerability Assessment of LightWeight Cryptographic Scheme, XOODYAK
Security
Hardware Security: Attack and Defense
Work-in-Progress Poster
Qubit Mapping Toward Quantum Advantage
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning*
EDA
RISC-V
Timing and Low Power Design
Research Manuscript
Robust Tickets Can Transfer Better: Drawing More Transferable Subnetworks in Transfer Learning
AI
AI/ML Algorithms
Front-End Design
Speeding-Up RISC-V GPGPU Accelerator using High-Bandwith Memory on FPGA
Front-End Design
RISC-V
Work-in-Progress Poster
VSAGE: an End-to-End Automated VCO-based ΔΣ ADC Generator
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Sessions
Research Manuscript
Practical EdgeAI Infrastructure and Applications: Efficiency and Resilience in the Wild
AI
RISC-V
AI/ML Application and Infrastructure
Research Manuscript
Unleashing the Power of Neural Networks through Hardware Acceleration
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Special Session (Research)
Will Heterogeneous Integration Drive the Next Phase of Moore's Law?
EDA