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Organization

Intel
Presenters
Anantha Krishnan A.K
Aniket Agrawal
Richa Agrawal
Lalit Arora
Ketan Baladaniya
Subrata Kumar Behera
Priyanka Bhagwat
Narendra Kumar Bhuma, Jaya
Amit Bleiweiss
Jagadeesh Boddu
Bob Brennan
Jeremy Casas
Wilson Chan
Bhrugurajsinh Chudasama
Samuel Coward
Sandeep Dappili
Debayan Das
Daniel Dinu
Theo Drane
Anil DSouza
Raj Dua
Pradeep Dubey
Joseph Friel
Jason Fung
Shobhit Kumar Garg
Aarti Gupta
Sivaramakrishnan Harihara Subramanian
Roger Hayward
Anshul Jain
Balaji Rao Jami
Matthew Jastrzebski
Lei Jiang
Sai Krishna Kairamkonda
Srim Karthik Kanneganti
Rajesh Karturi
Anmol Khatri
Kishore Kota
Rohit Kumar
Vinay Kumar
Souvik Kundu
Colin Landon
Alex Levin
Fulung (Andy) Li
Ravi Mahajan
Prabhakar Marepalli
Sankaran Menon
Vedprakash Mishra
Emiliano Morini
Harshal Mumbaikar
Manoj Kumar Munigala
Rohit Murarka
Sanjay Murthy
Narendra Nimmagadda
Daniel Pantuso
Madhu Pappu
Noel Pereira
Christopher Poole
Kiran Rampurkar
Sayak Ray
Sayak Ray
Ayan Roy Chowdhury
Santosh Santosh Ghosh
Mohammed Shahid
Manjunath Shamanna
Debendra Das Sharma
Pankaj Sharma
Vivek Sharma
Samichi Shrivastava
surinder sood
Narayan Srinivasa
Govinda Rajulu STG
Srinivasa R STG
Brahmaiah Throvagunta
Avinash Varna
Raghavendra Vasappanavara
Mike Wang
Wen Wang
Devendra Yadav
Jin Yang
Zhenkun Yang
Koby Zand
Ariela Zeira
Session Chairs
Ankit Gopani
Rajesh Jayashankara Shridevi
Suriyaprakash Natarajan
Sandeep Kumar Samal
Wen Wang
Presentations
Research Manuscript
$\mathbf{C^2PI}$: Crypto-Clear Private Inference
AI
AI/ML Security/Privacy
Special Session (Research)
A Scalable Formal Approach for Correctness-Assured Hardware Design
EDA
Back-End Design
Accelerated design convergence using automatic recipe tuning through Intel enabled AI-ML PnR framework
Back-End Design
Research Manuscript
AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
Design
AI/ML System and Platform Design
Work-in-Progress Poster
Automated feedthrough path generation and validation flow at RTL level based on floorplan aware specification of channel-less SoC
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
Automating Constraint-Aware Datapath Optimization using E-Graphs
EDA
RTL/Logic Level and High-level Synthesis
Engineering Track Poster
Bridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics Designs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
CANCELED - Auto-Detection and Unraveling the reasons for the Unoptimized Nets
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
CANCELED - Deriving Optimal Unique Multi Instances In Large SoCs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
CANCELED - Early IR Drop Prediction using Machine Learning for Power Grid
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
CANCELED - Minimum System Voltage Prediction for Server Processor based on Machine Learning in Post Silicon
Front-End Design
RISC-V
Back-End Design
CANCELED - Thermal aware Vectorless EM/IR signoff for High Speed Custom Digital IPs
Back-End Design
Research Manuscript
Comprehensive Integration of Hyperdimensional Computing with Deep Learning towards Neuro-Symbolic AI
Design
Emerging Models of Computation
Special Session (Research)
Compute Express Link (CXL*): Open Interconnect for Cloud Infrastructure
AI
Cloud
IP
Delivering on RISC V's Promise to Give Designers Freedom to Innovate – What's Needed?
IP
RISC-V
Front-End Design
Design for Verification - Case Reopened
Front-End Design
Engineering Track Poster
EM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Transformative Technologies Theater
Enabling AI at Zettascale: Wafers, Chiplets, or both?
IP
Everything You Should Know about UCie
IP
Engineering Track Poster
FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Formal Verification of Floating-Point Matrix Multiply-Add Designs
Front-End Design
RISC-V
Front-End Design
Formal Verification: First Line of Defense for Securing your Hardware from Attacks
Front-End Design
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
HW Security Path Validation Using Formal Methods: Intel Case Studies
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Integration of Intel Thermal Model with Design-for-Reliability Flow
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Transformative Technologies Theater
Intel PowerVia design considerations to optimize SOC design
Research Panel
Is Deep Learning Computationally Sustainable?
AI
Engineering Track Poster
Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Novel Numerical Hardware Design Methodology: From machine readable specification to optimized RTL
Front-End Design
Engineering Track Poster
Optimal MSCTS Driver duplication for improved H-Tree Clock Skew and Insertion delay
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Manuscript
Power Side-Channel Vulnerability Assessment of LightWeight Cryptographic Scheme, XOODYAK
Security
Hardware Security: Attack and Defense
Special Session (Research)
Pre-Silicon security assurance for SCA and FI: an industry perspective
Security
Back-End Design
Predictive Crosstalk Fixing Using XGBoost Regressor​
Back-End Design
IP
Reduced Layout Closure TAT and Compute Resources by Accelerating DRC Signoff Analysis through an Incremental Approach
IP
Engineering Track Poster
RV (Reliability Verification) Automation To Improve Execution Efficiency
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
The anatomy of incremental floorplanning solutions
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Manuscript
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
EDA
Design Verification and Validation
Sessions
Special Session (Research)
Toward Provably Correct Hardware Accelerator Design: Perspectives, Opportunities, and Challenges
EDA
Research Manuscript
Circuit Design Potpourri
Design
AI/ML, Digital, and Analog Circuits
Front-End Design
The Next Frontiers in the Front End
Front-End Design
RISC-V
Research Manuscript
Design for Manufacturing: Make It or Break It
EDA
Design for Manufacturing and Reliability
Research Manuscript
Let's Get with the Processing-in-Memory Program
Design
In-memory and Near-memory Computing Architectures, Applications and Systems