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Organization

Ansys
Presenters
Geethu Babu
Prith Banerjee
Murat Becer
Norman Chang
Sreeja Chowdhury
Ed Deeters
Bernard Dion
Yongsheng Guo
Zhongming Hou
Amit Jangra
Koshy John
John Lee
Lang Lin
Jeff Linn
Chidambaram Rakkappan
Boris Shapiro
Xiaodong Wang
Larry Williams
Li Yahui
shuqiang zhang
Chang Zhao
Li Zou
Presentations
Engineering Track Poster
A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
A Novel Fitting Method of Package Material Parameters Base On MOP
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
Achieving Verifiable Autonomy: Is Design Automation the Golden Key?
Autonomous Systems
Engineering Track Poster
Aggressor Aware Design for Better IRdrop Results
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Transformative Technologies Theater
Are We There Yet? From Cloud-compatible to Cloud-optimized
Cloud
Engineering Track Poster
Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
DAC Pavilion Panel
Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
EDA
Embedded Systems and Software
Designing Effective Autonomous Systems and Digital Twins
Embedded Systems
Keynote
Visionary Talk
Driving Engineering Simulation and Design with AI/ML
DAC Pavilion Panel
Is Systems Engineering the solution to the limits of Dennard Scaling and Moore's Law?
Design
Engineering Track Poster
Novel Chip-Package-System thermal analysis with RTL Power
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Packaging and Manufacturing Technologies save the day!
Back-End Design
Engineering Track Poster
Power Integrity analysis of 3D stacking Structure in CMOS Image Sensor Chip
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Back-End Design
Embedded Systems
Front-End Design
IP
Tutorial
Side-Channel Analysis: from Concepts to Simulation and Silicon Validation
Security
Engineering Track Poster
SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V