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Organization

Huawei
Presenters
Renzo Andri
Haitham Bou Ammar
Lukas Cavigelli
Lei Chen
Aiguo Cui
Wenchao Ding
Antoine Grosnit
Fred Han
Zhigang Huang
Camille Jalier
Shangling Jui
Xing Li
Xing Li
Wei Lu
Bowen Pang
Enrico Reggiani
Mohammad Salameh
Weihua Sheng
Jiyuan Shi
Rasul Tutunov
Yifei Wang
Dmitry Yakimets
Mingxuan Yuan
Lubo Zhang
Matthieu Zimmer
Mengchuan Zou
Presentations
Research Manuscript
A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
EDA
RTL/Logic Level and High-level Synthesis
Back-End Design
Achieve Dataflow and Global Placement Coherence using Virtual Object Constraint
Back-End Design
Work-in-Progress Poster
Applying Graph Explanation to Operator Fusion
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Research Manuscript
DriverJar: Lightweight Device Driver Isolation for ARM
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation
Design
AI/ML Architecture Design
Engineering Track Poster
Global Placement Exploiting Standard Cell Merging Constraint for Effective Semi-custom Design Optimization
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Manuscript
HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Layout Decomposition via Boolean Satisfiability
EDA
Design for Manufacturing and Reliability
Research Manuscript
Lightweight Structural Choices Operator for Technology Mapping
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
Design
AI/ML System and Platform Design
Research Manuscript
STCG: State Aware Test Case Generation for Simulink Models
EDA
Design for Test and Silicon Lifecycle Management