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Organization

Samsung Electronics
Presenters
Cheoljun Bae
YoungHoe Cheon
YoungRye Cho
Byul Choi
HONGSEOK CHOI
Jaeseung Choi
Jeehoon Choi
Jung Yun Choi
Seonil Choi
Joohee Choung
NAYA HA
Changho Han
Kyoungman Han
Jeongwoo Heo
Sunik Heo
Jiwoo Hong
Yongjin Hong
Andy Hoover
Bosun Hwang
Kwangok Jeong
Saebit Jeong
Seolgyeong Jeong
Seonghun Jeong
Hye Rim Ji
Manwhee Jo
Youngrog Jo
Minho Jung
Hyunjoon Kang
Jaehyeon Kang
Jongku Kang
Kunhyuk Kang
Kwonchil Kang
Daero Kim
Doyun Kim
Heeju Kim
Hyundon Kim
Hyungock Kim
Hyunjin Kim
Jong Seong Kim
Jongho Kim
Ki-Ok Kim
Kihoon Kim
Kyoungbum Kim
Minkook Kim
Moonsu Kim
SANGYUN KIM
Taehun Kim
Taehwan Kim
TAEIL KIM
Wojoo Kim
Wooil Kim
Wook Kim
Youngsik Kim
Kevin Klein
Taehwa Ko
BonHyuck Koo
Sungung Kwak
Byunghoon Lee
Byunghyun Lee
Daehee Lee
Ingeol Lee
Inryoul Lee
Jaeho Lee
Jeonggu Lee
Jeongho Lee
Jingon Lee
Keunsoo Lee
Kyurae Lee
Mintae Lee
Yelim Lee
Yongseok Lee
Youngchan Lee
Heejae Lim
Jaeyoung Lim
Mijeong Lim
Heungchul Oh
Youngmin Oh
Beomchan Park
Hyungtae Park
Jongseong Park
Sangdo Park
Seonghyeon Park
Seunghyeon Park
Jongwoo Ryu
SK Ryu
Hyunseung Seo
Jaemin Seo
Jaewoo Seo
Jun Seomun
Ji Young Shin
Seongkyun Shin
Jaeyoung So
Woojoo Space
Ranjith V R
Hyunjae Woo
Jisu Yang
Jimin Yeo
Dongyoun Yi
Kiwon Yoon
Jinsuk Youn
Suhyun Yun
Presentations
Engineering Track Poster
3D IC Inter-Die Test Implementation Using IEEE1838
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
3DIC Design floorplanning flow and Early Area Estimation for Area optimization
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
A Novel Solution for 3nm/4nm and Below LVS Challenges: Local Layout Effects Extraction QA in LVS Rule Deck
Back-End Design
Work-in-Progress Poster
A Stand-alone Virtual Platform Runnable at Unified Time Domain as NVMe SSD Full-System Simulator
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Work-in-Progress Poster
Accurate and Fast Method to Close Design vs Silicon Gap
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Back-End Design
Aging-aware Static Timing Analysis with timing arc-level modeling
Back-End Design
Engineering Track Poster
Automated Design-aware optimized Fill Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Automated MIMCAP insertion solution for Turn-Around-Time Reduction
Back-End Design
Engineering Track Poster
CANCELED - DLA Circuit Optimization for Area and Power Reduction through Double-Height Metal-Lesser Adder Cells
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
CANCELED - Turnaround time/compute reduction for 3DIC Timing signoff
Back-End Design
Engineering Track Poster
Capturing Statistical Characteristics of High-Sigma Reliability Analysis Methods
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Classification of Clock Domain Crossing (CDC) Data using Machine Learning
Front-End Design
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Considerations for Accelerating and Efficient Use of Chip Design in the Cloud
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Dynamic CDC(Clock Domain Crossing) for Memory Design
IP
Front-End Design
Emulation Based Automation Platform For SoC Performance Verification
Front-End Design
Front-End Design
Full SoC power analysis and estimation with end-user software early in the design cycle
Front-End Design
Engineering Track Poster
Hierarchical Power Grid Analysis for 3D-IC
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Improved Peak Power Interval Detection using the Sliding Window Power Profile (SWPP)
IP
RISC-V
Back-End Design
IR-Drop Aware Power Layout Optimization Methodology for Full-Custom Design
Back-End Design
Work-in-Progress Poster
LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Engineering Track Poster
Learning Box Model using DSO.ai
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Low Power DTCO of FINFET Logic Process for Stacked CMOS Image Sensor
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
ML Based DRV Prediction and Optimization for DTCO
Back-End Design
IP
ML-based High Sigma Verification Methodology: SVS Methodology
IP
RISC-V
Front-End Design
Node Based Clock Gating: Reducing NoC Power in Low Bandwidth Scenario
Front-End Design
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Novel Hierarchical IREM Sign-off Flow using ROM
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Over-Design Methodology for Operating Voltage Minimization
Back-End Design
Engineering Track Poster
Path Tracer for Tr.-level STA Setup using Synopsys NanoTime
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
PBR Bank Conflict Avoidance Scheduling to enhance DRAM bank utilization
IP
Engineering Track Poster
Performance And Power Optimizing Method By Controlling Nano-Sheet Usage
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
RF Simulation Methodology in S-parameter & Periodic Steady State & Phase Noise Analysis
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Work-in-Progress Poster
ROC-DRAM: Low Latency and Low Power DRAM using Rows with Opposite Charging
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Work-in-Progress Poster
RODOS: Robust Design Optimization with Simulator Learning
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Front-End Design
Sophisticate Performance Verification Of SOC BUS By IP-XACT And Model
Front-End Design
Engineering Track Poster
SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Unique metric driven vector qualification and Ranking for peak power coverage
Front-End Design