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Organization

Synopsys
Presenters
Amzie Adams
Lokesh Ahuja
Rob Aitken
Luca Amaru
Asheesh Baghel
Asheesh Baghel
Nitin Bansal
Sachin Bansal
Suresh Barla
Mike Borza
Wenwen Chai
Wenwen Chai
Abhijeet Chakraborty
Wei-Ting Chan
Evan Chen
Charles Chiang
Sabya Das
Sabya Das
Sabya Das
Li Ding
Li Ding
Dhananjay Dubey
Haowen Fang
Nelly Feldman
Nivin George
Amit Goldie
Badri Gopalan
Satish Govindappa
Deyuan Guo
Avinash Gupta
Nupur Gupta
Sangwoo Han
Paras Jain
Praveen Jakki
Himanshu Kathuria
Vishal Keswani
Aftab Khan
Vishal Khandelwal
Jesse Kim
Jimmy Kim
Joon Kim
Kailash Kumar
Manoj Kumar
Sudipto Kundu
Myoungjun Kwak
Bob Lefferts
Michael Martin
Anurag Mittal
Ribhu Mittal
Mohan Mohan
Hari Mony
ayhan mutlu
Rohit Kumar Ohlayan
Vrinda Padmakumari
SB Park
Chirag Patel
S R Pavitra
Satyanarayana Prasad Patnala
Gaurav Pratap
Edward Pyo
Vishwajith Rao
Viraj Rawal
Bhargav S
Ruijing Shen
Rakesh Shenoy
Prateek Singh
Ki-jin Song
Akhil Thotli
Vistrita Tyagi
Piyush Verma
Rayson Yam
Yervant Zorian
Session Chairs
Luca Amaru
Maheshwar Chandrasekar
Sabya Das
Karthi Duraisamy
Haowen Fang
Nelly Feldman
Jucemar Monteiro
Saurav Nanda
Ganapathy Parthasarathy
Eleonora Testa
Zheng Zhao
Presentations
Engineering Track Poster
3D IC Inter-Die Test Implementation Using IEEE1838
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Work-in-Progress Poster
Accurate and Fast Method to Close Design vs Silicon Gap
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
IP
Advanced DFT method using Checker and Indication FFs on Automotive NAND Flash Memory
IP
Back-End Design
Aging-aware Static Timing Analysis with timing arc-level modeling
Back-End Design
Engineering Track Poster
Clustering of Assertions using ML/AI in Formal Verification
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization
Back-End Design
Embedded Systems
Front-End Design
IP
Front-End Design
Convergence Experiment: Closed Loop Data-Sense Qualifier-Based Bus Synchronizer to Overcome Convergence Violations in Clock Domain Crossings
Front-End Design
RISC-V
Front-End Design
Design for Verification - Case Reopened
Front-End Design
IP
Everything You Should Know about UCie
IP
Engineering Track Poster
Fast and Reliable IO Ring Checker for Ensuring ESD Robustness and Power Integrity Compliance of SOC design
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Hardware and Software Technologies continue to advance, in close collaboration
Back-End Design
Engineering Track Poster
High Performance, Scalable and Cost Optimized AWS Cloud Infrastructure for Chip Development.
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
High-Level Synthesis: Now is the time or will it continue to remain just a promising technology?
EDA
Back-End Design
Implementation Challenges in complex 3D/heterogeneous architectures
Back-End Design
Engineering Track Poster
Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
IO Designs for reliability in advanced technology nodes
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Learning Box Model using DSO.ai
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Manuscript
Lightning Talk: Latest Trends in Industrial Logic Synthesis
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Lightning Talk: Lithography and advanced technologies work together to deliver the foundry's needs
EDA
Design for Manufacturing and Reliability
Research Panel
Lost in Silicon: The Need for Re-Innovating the Future of Trusted Hardware and Supply Chain Resilience
Security
Research Manuscript
Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
AI
AI/ML Algorithms
Back-End Design
Over-Design Methodology for Operating Voltage Minimization
Back-End Design
Back-End Design
Packaging and Manufacturing Technologies save the day!
Back-End Design
Engineering Track Poster
Paradigm Shift in Power Aware Simulation Using Formal Techniques
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning*
EDA
RISC-V
Timing and Low Power Design
IP
Securing IP in the Cloud
Cloud
IP
IP
Shift Left Detection of Logic Equivalence Abort Points via RTL Linter
IP
Engineering Track Poster
Special Bit Pattern Injection in Simulation Verification by leveraging Formal Verification
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
The Art of Breaking Things Down - Hierarchical Abstraction for Power Sensitive SoC Signoff
IP
Transformative Technologies Theater
The Good, Bad and Cloudy
Cloud
Front-End Design
Verification Beyond Coverage
Front-End Design
IP
Weak Link Detection in Memory Periphery using Design Robustness Analysis
IP
Research Panel
Where Will AI Change EDA: Inside, Outside or Not At All?
AI
EDA
Sessions
IP
Everything You Should Know about UCie
IP
Research Manuscript
The Crossroad of AI Paradigms: From Neurons to Bits
AI
AI/ML Algorithms
Research Manuscript
Leading Developments from the Frontier of High-level Synthesis and Neighborhoods
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Greetings from Hardware-friendly AI Algorithms
AI
AI/ML Algorithms
Research Manuscript
When Bio-inspired Models Met Hardware Optimization
Design
Emerging Models of Computation
Back-End Design
Hardware and Software Technologies continue to advance, in close collaboration
Back-End Design
Research Manuscript
Everything, EveryPLACE, All at Once!
EDA
Physical Design and Verification
Special Session (Research)
Technological Advancements in the Quantum space – from Hardware Architecture to Computing Platform
Design
Research Manuscript
A Farewell to the Numerical Computing Paradigm
Design
Emerging Models of Computation
Research Manuscript
Progress from the Leading Edge of RTL Synthesis
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
This is Formal...But You Can Come Casual!
EDA
Design Verification and Validation
Research Manuscript
The Path to Reliable, Secure, and Energy-efficient Cloud-edge Continuum
Cloud
Design
Design of Cyber-physical Systems and IoT