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Organization

Cadence Design Systems, Inc.
Presenters
Shubham Agarwal
Neha Agrawal
Parul Agrawal
Shubham Agrawal
Xin Ai
Charles Alpert
Anunay Bajaj
Anunay Bajaj
Akshita Bansal
Stefano Basile
Tom Beckley
Hemlata Bist
Hua-Yu Chang
Lucas Chaves
Yi-Ting Chung
Craig Deaton
Ajit Gokhale
Matt Graham
Mehar Gupta
Preeti Gupta
Jing Hu
Prayes Jain
Harshit Jaiswal
Neeraj Kaul
Kushal Koolwal
Rajat Kukreja
Ashwini Kulkarni
Vishesh Kumar
Yixing Li
Huigang Liao
Gary Lin
Zi-Shen Lin
Wen-Hao Liu
Hitesh Marwah
Rohit Mishra
KT Moore
Eamon O'Gorman
Jonhatan Olave
Janet Olson
Mrunal Pancholi
Krunal Amrutbhai Patel
Nehal Patel
Rushin Patel
Vishwa Prabhat
Prashanta Ranabijuli
Erik Seligman
Vedansh Seth
Shinyu Shiau
Priyanshi Shukla
Bing-Xun Song
Lip-Bu Tan
Yueh-Hsin Tu
Mahesh Turaga
Harshdeep Verma
Bhupendra Vishwakarma
Stephanie Youssef
Badrinarayan Zanwar
Mahesh Zanwar
Zhiyu Zeng
Session Chairs
Prabal Basu
Presentations
Front-End Design
A Leap Forward in Architectural Formal Convergence Using Automated Case Splitting
Front-End Design
RISC-V
Engineering Track Poster
A Method to Plan & Generate IO Ring based on CSV Specifications
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Accelerating Datapath Verification using Formal techniques
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Addressing Common Verification Pitfalls of Chiplet Interconnects
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Keynote
Visionary Talk
Advancing Precision Medicine through Generative AI-driven Drug Development
DAC Pavilion Panel
Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
EDA
Hands-On Training Session
Build a Cadence Burst-to-Cloud workflow with NetApp “Design Anywhere” on AWS
Cloud
Embedded Systems and Software
Chiplets – The New Frontier of Electronic Design! Challenges and Solutions in Chiplet-based Designs
Embedded Systems
Engineering Track Poster
Credit Based scheduling for Precision time protocol frames in Automotive Ethernet
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Credit Based scheduling for Precision time protocol frames in Automotive Ethernet.
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Manuscript
DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
EDA
Timing and Low Power Design
Engineering Track Poster
Efficient way of Migration & Comparison of Custom IC Schematic Designs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Fast and Accurate Phase Noise Analysis of Crystal Oscillator in 28 FDSOI Process
IP
Engineering Track Poster
Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
High-Level Synthesis: Now is the time or will it continue to remain just a promising technology?
EDA
Hands-On Training Session
Increase throughput and productivity with Cadence tools in the cloud using flexible AWS compute choices
Cloud
Research Manuscript
Lightning Talk: Feasibility Checking for Advanced Packaging
EDA
Physical Design and Verification
Engineering Track Poster
Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Packaging and Manufacturing Technologies save the day!
Back-End Design
Engineering Track Poster
PHY Verification IP
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Preventing Iterations from SoC Implementation Stage by Developing Pin Accessible Standard Cell Library
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Tutorial
Reinforcing Circuit and Layout Synthesis
AI
EDA
Engineering Track Poster
Schematic aware IP Compiler : Improving Productivity with Relative Placement
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Security, Timing Synchronization, and Power Saving for Automotive Ethernet: Functional Verification Challenges and Its Solutions
IP
RISC-V
Engineering Track Poster
Statistical OCV based Design Closure
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Transformative Technologies Theater
The Good, Bad and Cloudy
Cloud
DAC Pavilion Panel
The Industry 4.0 Revolution of Semiconductor Design
Design
Front-End Design
Verification Beyond Coverage
Front-End Design
Engineering Track Poster
Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
Where Will AI Change EDA: Inside, Outside or Not At All?
AI
EDA
Sessions
Research Manuscript
Let's Network with Chiplets
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package