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Organization

STMicroelectronics
Presenters
Chirag Agarwal
Frederic AVELLANEDA
Ankur Bal
Francesco Battini
Ambika Bhardwaj
Atul Bhargava
Marco Castellano
Manvi Dhawan
Enea Dimroci
Anil Dwivedi
Jean-Arnaud Francois
Livio Fratantonio
Harsh Garg
Gaurav Goel
Chiranjeev Kumar Grover
Riccardo Guglielmo
Rohit Kumar Gupta
Rohit Kumar Gupta
Shashank Gupta
Alessandro Iannuzzi
Massimiliano Innocenti
Nitin Jain
Sanjeev Jain
Avinav Joshi
Ashish Kumar
Manish Kumar
Sahil Kumar
Marco Leo
Sebastien Marchal
Etienne Mauirn
Priya Meharde
Marco Meuli
Olivier Minez
Anand MISHRA
Anil Nagendra
Govind Pal
Lippika Parwani
Samant Paul
Mihir Pratap
Roberta Priolo
Anuradha RAY
Antonino Russo
Davide Sanalitro
Aditya Sharma
Amit Singh
Bhupendra Singh
Raghubeer Singh
Rajeev Singh
Rupesh Singh
Vikram Singh
natish Singla
Sharmistha SINHA
SAURABH SRIVASTAVA
Emilio Stante
Harshil Niranjanbhai UPADHYAY
Anil Yadav
Huqing Zheng
Presentations
Engineering Track Poster
A design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changes.
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
A Digital Emulator for an Analog Continuous Time Sigma Delta Modulator
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
A Method to Plan & Generate IO Ring based on CSV Specifications
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
A Novel IP for Real Time DC Estimation and Removal
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
An automated flow for High Performance Asynchronous Digital Controllers
Front-End Design
Engineering Track Poster
An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Automated Clock Analysis, Skew Group Generation & CT Verification
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Comprehensive Validation Solution for Silicon IP&Library
IP
RISC-V
Engineering Track Poster
Design For Testability in Asynchronous Digital Controllers : An automated flow to design and validate asynchronous logic for digital controllers
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Digital Design Flow for Area-Constrained IPs Using Custom Non-standard IEEE-754 Format​
IP
IP
Fast and Accurate Phase Noise Analysis of Crystal Oscillator in 28 FDSOI Process
IP
Engineering Track Poster
Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Hazard Detection Tool in Asynchronous Finite State Machines Transition Logic
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Low power DAC sub-system for Digital Beam Forming Chip
Front-End Design
Engineering Track Poster
Preventing Iterations from SoC Implementation Stage by Developing Pin Accessible Standard Cell Library
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Quality Assurance of DRC deck by QA Cell Methodology and Automation using Cadence Skill
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Requirement tracing for Design Flow in communication protocols IP
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Requirements Management Flow on Digital Projects with ReqTracker
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Using Machine Learning to Optimize and Accelerate Random Regression Testing
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Weak Link Detection in Memory Periphery using Design Robustness Analysis
IP