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Organization

Siemens EDA
Presenters
Mohamed Alimam
Amir Attarha
Divya Bareja
Minsub Byun
Keerthikumara Devarajegowda
Amit Dey
Parul Dohare
Mohammed Fahad
Matthieu Fillaud
David Fritz
Gaurav Garkoti
Tony Hemmelgarn
Salaheddin Hetalani
Joe Hupcey III
Mahima Jain
Craig Johnson
Craig Johnson
Vishnu Kanwar
Vishal Kashyap
Russell Klein
Manish Kumar
Sachin Kumar
Justin Lee
Sungyoun Lee
William Lee
Mark Malinoski
Tony Mastroianni
Dina Medhat
SungJin Moon
Gerardo Nahum
Ronan Poirier
Bhupesh Prajapat
Siddharth Ravikumar
Kevin Rinebold
khaled Salah
Ahmed Saleh
Joseph Sawicki
Yohan Seo
Peter Shields
Sasa Stamenkovic
Steve Sunter
Wei Tan
Vijay Tayal
Pradeep Thiagarajan
Andres Torres
Nicolae Tusinschi
BK Yoon
Session Chairs
Dave Rich
Joseph Shinnerl
Presentations
Engineering Track Poster
A Data Analytics Based Approach for Reducing Clock Tree Power at RTL
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
A Novel Solution for 3nm/4nm and Below LVS Challenges: Local Layout Effects Extraction QA in LVS Rule Deck
Back-End Design
Engineering Track Poster
A Statistical approach to identify wasted power consumption in combinational clusters
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Advanced transceiver components for robust handling of signal noise and loss
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
An efficient methodology to verify floating point matrix multiplication
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Automated Design-aware optimized Fill Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
DAC Pavilion Panel
Best of Both Worlds – Bridging the Gap between EDA, System and Manufacturing
EDA
Engineering Track Poster
Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
IP
Comprehensive Validation Solution for Silicon IP&Library
IP
RISC-V
RISC-V Zone
Creating Domain Specific Accelerators for RISC-V Designs with Siemens EDA
Front-End Design
Crossing the RISC-V customization barrier with formal
Front-End Design
RISC-V
Engineering Track Poster
Deep learning Platform for FSM-Based HLS
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
DAC Pavilion Panel
Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
Design
Front-End Design
Design for Verification - Case Reopened
Front-End Design
Embedded Systems and Software
Designing Effective Autonomous Systems and Digital Twins
Embedded Systems
Front-End Design
Full SoC power analysis and estimation with end-user software early in the design cycle
Front-End Design
Research Manuscript
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
EDA
Design Verification and Validation
Research Manuscript
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Signal/Power Integrity Benefits
Design
AI/ML, Digital, and Analog Circuits
IP
Improved Peak Power Interval Detection using the Sliding Window Power Profile (SWPP)
IP
RISC-V
DAC Pavilion Panel
Is Systems Engineering the solution to the limits of Dennard Scaling and Moore's Law?
Design
IP
ML-based High Sigma Verification Methodology: SVS Methodology
IP
RISC-V
Back-End Design
Packaging and Manufacturing Technologies save the day!
Back-End Design
RISC-V Zone
Removing the Risk from RISC-V using the RISC-V Trace Standard
Transformative Technologies Theater
Simplifying Success in the Cloud
Keynote
Visionary Talk
Systems 2030 – What’s Needed to Succeed in the Next Decade of Design without Resorting to Human Cloning
Transformative Technologies Theater
The Good, Bad and Cloudy
Cloud
Sessions
Front-End Design
Dragging Debug into a New Era
Front-End Design
Research Manuscript
Everything, EveryPLACE, All at Once!
EDA
Physical Design and Verification