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Organization

KU Leuven
Presenters
Josep Balasch
Stefan De Gendt
Enrique Dehaerne
Georges Gielen
Vikram Jain
Giuseppe Sarda
Josse Van Delm
Maarten Vandersteegen
Ingrid Verbauwhede
Ingrid Verbauwhede
Marian Verhelst
Presentations
Work-in-Progress Poster
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Engineering Track Poster
A Machine Learning Approach Towards SKILL Code Autocompletion
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
DAC60 Celebration Panel: Designing the Future
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Embedded Systems
RISC-V
Embedded Software
Research Manuscript
Lightning Talk - Novel Techniques in Synthesis and Verification of Analog Circuits
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
On the unpredictability of SPICE simulations for Side-channel Leakage Verification of Masked Cryptographic Circuits
RISC-V
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
Design
AI/ML System and Platform Design