Close
 

Organization

Texas Instruments
Presenters
Jaaneshwaran A
Krishna Allam
Aswin B
Lakshmanan Balasubramanian
Vishal Bhadauria
Tanushri Bhagat
Nitin Bisht
Bhavya Sri Dasari
Chandra Has Dondapati
Penchal Kumar Gajula
Subhadeep Ghosh
Sai Ram Jayanthi
Ayush Jodh
Ninad Khire
Aruna Koityar
Gaurav Kumar
Sidhartha Kumar
Ankitha M
Pooja Madhusoodhanan
Ajoy Mandal
Harish Maruthiyodan
Arif Mohammed
Ankita Mohanty
Subham Mohapatra
Prasanth Kumar Narava
Ashwini Padoor
Abhinav Parashar
Rith Pok
Karthik Rajakumar
Parthasarathy Ramesh
Kaustav Ray
Raj Sankaralingam
Prashanth Saraf
Ruchi Shankar
Yogeshwaran Shanmugam
Sanjay Singh
Shane Stelmach
Karthik Subburaj
Gaurav Varshney
Prasanth Viswanathan Pillai
Presentations
Engineering Track Poster
Accelerating Datapath Verification using Formal techniques
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Back-End Design
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Automation Framework Based IP/Subsystem Integration Verification in SoC - A Systematic Approach for Integration Quality Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Efficient methodologies for STL certification of Spinoff SOC designs.
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Front-End Design
Power Intent Automation for Ultra Low Power Mixed-Signal SoC
Front-End Design
Engineering Track Poster
Solving the randomization challenge in CPU verification
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Engineering Track Poster
Statistical OCV based Design Closure
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Back-End Design
System Power Integrity Analysis: from the PMIC to the Transistor
Back-End Design
Engineering Track Poster
Unified Design Verification Flow for Pre-Silicon SoC Power Estimation And Achieving Post-Silicon Correlation to Customer Sampling
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V