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Organization

AMD
Presenters
David Akselrod
Ravindra Ayyagari
Ramki Balasubramaniam
Ivo Bolsens
Amitabh Das
Amit Gupta
Animesh Jain
Vidhu Joshi
Emrah Karagoz
Wuxi Li
Soon-Huat Lim
Gabriel Loh
Srilatha Manne
Alexander Pivovarov
Andrew Ross
Mehdi Sadi
Phil Steinke
Krishnan Sukumar
Santosh Vodnala
Scot Weber
Session Chairs
David Akselrod
Vidyasagar Ganesan
Amit Majumdar
Presentations
Special Session (Research)
Advanced Packaging and Integration: It's Not Enough
EDA
Special Session (Research)
AI Software Is Leading the Hardware Development in Cloud Computing
Cloud
Transformative Technologies Theater
Ask Me Anything with Ramki Balasubramaniam
Cloud
Front-End Design
Design for Verification - Case Reopened
Front-End Design
Front-End Design
Dragging Debug into a New Era
Front-End Design
Research Manuscript
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
EDA
Design Verification and Validation
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Implementation Challenges in complex 3D/heterogeneous architectures
Back-End Design
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
Pre-Silicon Power Side-channel Security Verification for Crypto IPs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
SILICON DEBUG OF REAL TIME CLOCK MACRO USING NANOPROBING TECHNIQUE
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V
Research Panel
Sustainable Autonomous Systems Design
Autonomous Systems
Transformative Technologies Theater
The Good, Bad and Cloudy
Cloud
Research Panel
Where Will AI Change EDA: Inside, Outside or Not At All?
AI
EDA
Sessions
IP
Advanced Front-End Verification Methodologies for Leading-Edge IP
IP
RISC-V
Front-End Design
Design for Verification - Case Reopened
Front-End Design
Research Manuscript
Breaking the Fault and Yield Barriers
EDA
Design for Test and Silicon Lifecycle Management