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Organization

Fraunhofer IIS/EAS
Presenters
Andy Heinig
Benjamin Prautsch
Presentations
IP
Automatic Chiplet Interface IP Generation Across Technology Nodes, Vendors, and Stacks Using Intelligent IP
IP
Engineering Track Poster
Automatic Generation of 22FDX® OpAmp Designs in the Virtuoso® Suite by Incorporating ID-Xplore™ for Sizing with IIP Layout Generators
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V