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Organization

ETH Zürich
Presenters
Luca Benini
Thomas Benz
Maciej Besta
Matheus Cavalcante
Tim Fischer
Torsten Hoefler
Patrick Iff
Lana Josipovic
Andreas Kurth
Onur Mutlu
Arpan Suravi Prasad
Carmine Rizzi
Michael Rogenmoser
Hanyu Wang
Yunan Yang
Presentations
Work-in-Progress Poster
A cost-generic logic synthesis framework with customizable cost functions
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security
Special Session (Research)
Accelerating Genome Analysis via Algorithm-Architecture Co-Design
Embedded Systems
Research Manuscript
An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Embedded Systems
RISC-V
Embedded Software
Research Manuscript
Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning
AI
AI/ML Algorithms
Research Manuscript
PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
Design
AI/ML System and Platform Design
Research Manuscript
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-Flexibility AR/VR Processing
Design
RISC-V
SoC, Heterogeneous, and Reconfigurable Architectures
Workshop
SSH-SoC: Security and Safety in Heterogeneous Open System-on-Chip Platforms
Security