Presentation
Thermal Aware On-Die Electrical Analysis
DescriptionThe nonuniform thermal profile and process variations are two major concerns in the present-day VLSI designs. To correctly predict performance, leakage/reliability measures and address any issues during the early stages of design phases, it is desirable to have a reliable thermal estimation of the chip. However, the leakage power sources vary greatly due to process variations and temperature, which result in significant variations in the hotspot and thermal profile formation in VLSI chips. In this paper, the thermal analysis and temperature aware EM/IR analysis of the die has been done. Two things are investigated or analyzed, namely, temperature profile of the die and temperature-based EM/IR. The accuracy of the analysis is validated by comparing simulated data and Silicon data.
Presenter
Event Type
Back-End Design
TimeMonday, July 10th11:00am - 11:15am PDT
Location2008, Level 2
Back-End Design