High Bandwidth Memory (HBM3-7.2Gbps) 2.5D-IC Integration with Signal Interconnects and Power Distributed Networks Design-Optimization
DescriptionFor 5G/AI and HPC applications, 2.5D/3D-IC high speed chiplets integration with high bandwidth memory (HBM) has been a critical demand in recent years. To achieve this demand, HBM3 specification was emerged in 2016. Its total data throughput can be up to 922GB/s and with per data lane up to 6.4-7.2GT/s, than that of HBM2E by 512GB/s.

This work demonstrates an 2.5D-IC solution through GUC and tsmc collaboration project, implemented at advanced package technology platforms, i.e., silicon interposer (CoWoS-S) and RDL interposer (CoWoS-R), respectively. Its design-optimization consists of signal integrity at HBM3 high speed silicon interconnections and power integrity at whole power distributed networks & decoupling strategy. For silicon correlation, this work is implemented at silicon technology of HBM3 PHY in 7nm, and CoWoS® silicon interposer in 65nm.

Moreover, to achieve SI/PI design performance requirement for HBM3-7.2Gbps, Ansys electromagnetic EDA solution (HFSS, RaptorX, SIwave, Q3D) is employed at design phases for interconnects and PDNs post-layout analyses. With the aid of Ansys EDA, it can achieve HBM3 data lane eyewidth up to 0.52-0.68UI at CoWoS-S, and 0.68-0.79UI at CoWoS-R, as well as the maximum voltage drop (DC+AC) suppressed to less than 5% from supply voltages (both power domains, 0.4V and 0.75V).
Event Type
Back-End Design
TimeMonday, July 10th11:15am - 11:30am PDT
Location2008, Level 2
Back-End Design