CANCELED - Thermal aware Vectorless EM/IR signoff for High Speed Custom Digital IPs
DescriptionFor High Speed Mixed signal IPs, custom digital designs are prone to EM/IR issues due to high frequency paths and custom drawn layout. At the same time, testbench setup with worst case vectors is a big challenge along with coverage concern in such simulation based run. As an alternative, vectorless mode EM/IR provides desired coverage and worst case analysis for EM purpose. Even though EM/IR is covered through heuristic based approach in industry standard tools, there's no equivalent thermal solution to include Self heat effect for transistors. This paper talks about a novel characterization based approach to mitigate Self heat risks for above mentioned designs. As a part of the solution, vendor EDA tool runs a design specific transistor characterization with Simulation models to compute thermal resistance of each transistors. Later in the flow vectorless engine calculated power is used along with the derived thermal resistance to compute device deltaT profile used by Self heat analysis.
Event Type
Back-End Design
TimeMonday, July 10th11:30am - 11:45am PDT
Location2008, Level 2
Back-End Design