Presentation
Early Android Software Verification With RISC-V Virtual Platforms
SessionMicroFaaS Server-less computing, RISC-V virtual platforms, and flexible systems modeling platform.
DescriptionShift-left methodologies allow companies to release their products on time and bug-free by starting software verification even before physical hardware prototypes are available. For these, full system simulators, so called Virtual Platforms (VPs), need to be available to the software engineers as early as possible in the system design cycle. The matter is further complicated by the sheer size of modern software stacks consisting of millions of lines of code. To verify them extremely fast VPs are needed to cover all test cases in reasonable time and allow for interactive target software debugging.
RISC-V Android is a prime example of such a software stack. As the RISC-V patches were merged to the main Android repository in late 2022, it is very new and thus lacks some test mileage. At the same time more than 100 billion instructions need to be simulated for one Android boot. In this presentation, we showcase how we brought up Android 12 on our RISC-V simulator SIM-V and how it can be used for testing and debugging. SIM-V performs a full Android boot in less than 5 Minutes and offers deep introspection and debugging capabilities for interactive use as well as continuous integration.
RISC-V Android is a prime example of such a software stack. As the RISC-V patches were merged to the main Android repository in late 2022, it is very new and thus lacks some test mileage. At the same time more than 100 billion instructions need to be simulated for one Android boot. In this presentation, we showcase how we brought up Android 12 on our RISC-V simulator SIM-V and how it can be used for testing and debugging. SIM-V performs a full Android boot in less than 5 Minutes and offers deep introspection and debugging capabilities for interactive use as well as continuous integration.
Event Type
Embedded Systems and Software
TimeTuesday, July 11th1:30pm - 1:48pm PDT
Location2008, Level 2
Embedded Systems
RISC-V