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Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization

DescriptionProcess scaling cost is increasing faster than in the past, raising the cost of SoC products, while performance and power targets are getting tighter. On the other hand, due to silicon-to-spice error, the performance and power of Silicon falls short of the expected target. Modifying the design to solve this will cause a huge increase in production cost. As an alternative, it's possible to consider a silicon tuning method that achieves the target performance/power by moving the center of the FEOL/BEOL process target without changing design. However, it is still costly to find an optimization point considering complex parameter combinations by silicon wafer test. In this work, we propose a novel method to perform AI supported simulation to find FEOL/BEOL process sweet spot with reasonable runtime. Experimental result using 4nm CPU design shows that the proposed technique can find optimal process corner based on PPA needs.

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