Presentation
Statistical OCV based Design Closure
DescriptionWith increasing demands on improving power, performance and area in digital designs we are adopting design practices that are increasing variability and increasing the challenge of application of optimal design margins to account for process variations. Statistical on-chip variation (SOCV) is a technique that is able to handle these variations accurately. Cadence tools Genus , Innovus and Tempus have capabilities to enable SOCV based design closure. The availability of the through-the-flow optimization ensure better timing convergence. Accurate statistical analysis capabilities make the approach accurate for both base and crosstalk delay analysis. We have also found that capacitance modeling is playing a significant role in determining path level accuracy and have used 8-piece pin cap along with conditional pin cap modeling in characterization of standard cells to get the desired accuracy goals. We have tried to optimize the characterization cost of SOCV by enabling this technique only for corners with high variation and avoiding constraint characterization through SOCV. Finally we have also used the Parametric Timing Robustness (PTR) capability in Tempus to ensure that the closure process does not impact yield. We show results demonstrating accuracy of the technique as compared to SPICE. We have been able to use this technique to reduce design clock tree with 40% lower cell count and overall 44% lower hold buffer count which in turn significantly brought down standard cell area and power in a low power microcontroller design.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V