A Method to Plan & Generate IO Ring based on CSV Specifications
DescriptionTest chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. To ensure the quality of IPs, designers spend considerable time and effort in designing test chips for validation of precision analog circuits like PLLs. This calls for a solution that streamlines the test chip designing that would also be scalable for different technologies. Test chips need to be aligned with the testing board to ensure characterization closure of IP. The design typically involves generation of an IO ring within which macro-IP blocks and power rails are placed. Generation of this IO ring manually is very effort intensive, while ensuring DRC correct design. Usually, the Testchip Designer has specification for the size of PR Boundary, which fixes the placement of corner cells. The spacing between IO pads at each edge is fixed and user needs to fill the remaining area with filler cells. In the proposed flow, a methodology is developed based on a CSV XLS file capturing placement constraints to automatically generate schematic and layout initialization. The constraints are then used to create an IO ring automatically. The design is DRC correct by construction.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design