Floorplan for implementation methodology to the Next MSoT Smart Power (BCD) Designs
DescriptionIn today's dynamic scenario, the design complexity is increasing significantly for analog mixed signal designs as the technology moves forward so advanced methodologies are required to improve the quality of reliable products and increase globally the layout productivity for reducing the time to market.
For the Smart Power Designs due to few level metals for signal routing, aggressive voltage dependent rules and complex spacing table, a well-designed floorplan at early stage is the main key to save design area, close the chip-level routing avoiding congestion issues which makes PG tape to be released on time.
This new "Floorplan for implementation” flow is based on native Cadence capabilities (Design Planning and Analysis (DPA)”, "Design Intent”, Simulation Driven Routing) and dedicated STM customizations allow starting from excel/csv cells area estimation file to generate a Floorplan down to Implementation.
Our large automotive design community does have tight tapeouts schedule requiring designs steps saving wherever is feasible and this approach allows to meet the requirement to be on time to the market.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design