A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
DescriptionThe pursuit of high integration and high performance 3DIC design makes the number of cells per unit area of the chip increase and thermal coupling between cell is intensified. Meanwhile, with narrow 3-D fin structure and lower thermal conductivity in substrate, local FinFET device temperature is higher compared to planar MOS structure. In addition, the joule heat between wires in limited space becomes severe.
Narrower physical wires, higher current density, increasing impact of wire temperature on EM limit, all these factors can lead to rise of the chip temperature and worsen the electromigration(EM) phenomenon, such as open or short. To avoid function failure caused by reliability-related problems, designer restricts the design excessively with whole die set to a value higher than the maximum operating temperature in traditional flow, which causes difficulty to iterate and even failure to sign-off. So the accurate "Thermal aware EM sign-off" is a must for advanced 3DIC design.
Different from the traditional flow, our flow can model the realistic heat dissipation environment of the complicated 3DIC accurately, and meanwhile take the thermal coupling of the instance, and the wire-to-wire joule heat into account to analyze the thermal convergence process precisely. For different layers and locations, different temperatures (Tj) are generated. The realistic spatial tempatrue distribution scenario generated by system-level thermal analysis can replace the coarse global temperature setting in traditional EM analysis flow.
With the thermal-aware EM flow, we can avoid over-design and under-design. And the simulation results can be used to provide guidance for the heat dissipation design of the system.
keywords : thermal-aware, EM-analysis, boudary condiction, system-level
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall