Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
DescriptionIn the graphics processing unit (GPU)-accelerated system, there are two important communication links: one is GPU-GPU link and the other is GPU-high-bandwidth memory (HBM) link. In the current GPU-accelerated system, GPUs and HBMs communicate via copper-based electrical interconnects on a Silicon interposer. As the required workloads increase, data transmission between GPUs and between GPUs and HBMs have been evolving rapidly. One way to augment data transmission of GPU-to-GPU and GPU-to-HBM is to increase data throughput by increasing the number of electrical lanes. Another way is to enhance the data rate per each lane. However, because the electrical interconnects are copper-based, the extent to which the data transmission can be increased is limited by the physics of having to carry high-frequency signals. For example, signal integrity can be significantly degraded due to high-frequency losses and cross-talk noises. Also, longer electrical interconnects need for re-driver/re-timer circuits to maintain signal quality across the paths. As such, data transmission via copper-based interconnects may become more and more challenging. We address these problems by proposing a streamlined GPU architecture that leverages an integrated Silicon Photonics (SiPh) via an optical network-on-chip (ONoC) to interconnect GPUs and HBMs in future high-bandwidth GPU-accelerated systems.
Engineering Track Poster
TimeWednesday, July 12th5:43pm - 5:44pm PDT
LocationLevel 2 Exhibit Hall