Low Power DTCO of FINFET Logic Process for Stacked CMOS Image Sensor
DescriptionIn the stacked CMOS image sensor (CIS) process, logic process can be optimized for low power because of long battery life. This work presents design and technology co-optimization (DTCO) approaches for dynamic power reduction in CIS logic process. In order to reduce the dynamic power, we propose cell library and back-end metal optimization. Cell library optimization includes verifying high density (HD), ultra-high density (UHD) and high performance (HP) library with different cell heights and allowing metal 1 layer routing by changing cell architecture. Back-end metal optimization includes increasing the number of routing metal layers from 5 to 6 and adopting the lower dielectric constant material. Through DTCO approaches, HD library and 6 metal-stack with lower dielectric constant material are selected, and they can reduce dynamic power by 21.1% against reference.
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall