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Hierarchical Power Grid Analysis for 3D-IC

SessionTuesday Engineering Track Poster Reception

DescriptionAs a memory device is higher speed, lower power, more density and stacked, a robust Power Distribution Network(PDN) design is becomes key factor to success a memory device. Especially a robust PDN design of 3D-IC memory is important. For a robust PDN design, a chip designer run IR-Drop and Dynamic Voltage Drop(DVD) analysis to find and fix weak points. As a memory device size and a number of memory die in 3D-IC memory is increased, PDN size is also increased. So IR-Drop analysis run time is increased significantly. For fast IR-Drop analysis, IR-Drop analysis run time reduction is critical to verify PDN and to meet design schedule. In this paper, we proposed a hierarchical IR-Drop analysis for 3D-IC memory PDN based on a hierarchical methodology. The proposed method has 2 steps. In a setup step, PDN is partitioned and a macromodel of each PDN partition in top-level and die-level is made. In an analysis step, macromodel's port current, port voltage, and maromodel's internal node voltage are calculated in parallel. For fast hierarchical IR-Drop analysis, we propose an efficient macromodeling and port current/node voltage calculation method using Schur complement. And we implemented a parallel process using Message Passage Interface(MPI). The proposed method's experiment results show that IR-Drop analysis run time is reduced 64.5%(18.3Hr→6.5Hr) in 3-stacked 3D-IC memory device. In addition, the 9-stacked 3D-IC memory device, which was impossible by the traditional flat analysis methodology, was analyzed at 7.6Hr (+ DVD : 26.46Hr). The proposed methodology is expected to contribute for a robust 3D-IC memory PDN design.

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