Presentation
Automated Design-aware optimized Fill Methodology
DescriptionMetal fill is a mandatory step at advanced nodes to ensure manufacturability and high yield, but fill insertion affects timing, due to added capacitance. Balancing density requirements with timing on critical nets is crucial for both timely design closure and design reliability. Because RF/analog designs are especially sensitive to parasitic capacitive coupling between signals and fill, special handling for sensitive nets and devices is required. Manual identification of critical design elements (nets/devices) is error-prone and not scalable. We propose a methodology that automates identification of critical/sensitive nets and devices to minimize RC impact of fill on these nets during fill insertion, while still maximizing fill insertion ratios. Our methodology links design knowledge/awareness with optimized geometrical fill insertion without impacting design performance and reliability. Real-world results demonstrate the effectiveness and efficiency of our proposed methodology.
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V