Preventing Iterations from SoC Implementation Stage by Developing Pin Accessible Standard Cell Library
DescriptionAccessibility of pins in Standard Cells in development stage by running the SoC implementation router, as the std-cell layout development is done in custom environment and their abstracts are consumed at SoC implementation level, where issues in accessing pins of standard cells are discovered during Place and Route (P&R) flow. This is costlier in terms of efforts and time which can be overcome by using this tool during library development phase itself. There is need to ensure that standard cells are clean by construction for Pin accessibility during library development phase in Virtuoso.
Pin accessibility can be checked using varied and flexible standard cell placement topologies, utilisation, varied Top Metal Layer, by choosing various voltages, and variable critical net configurations to use double cut vias.
In this paper, we are discussing the methodology for pin accessibility check and integrated environment developed for quick use of SoC routing tool (Innovus) in custom environment (Virtuoso) to check pin accessibility in standard cells during library development stage itself. For creating SoC like scenario early in library development stage, we have developed different practical placement topologies of std-cells, considering different routing options to create congestion and using digital tool's technology LEF rules. The tool can report all routing statistics with DRC violation if any because of accessibility issue of standard cell pin. Corrections can be made after analysing the output reports.
The above integrated environment is called Pin Accessibility Checker (PAC). By deploying this integrated tool and methodology, all errors caught systematically. The solution is fast and comprehensive, cost of implementing the quality check is very less compared to the gains achieved. The method is used across all process technologies on all deliverable standard cell libraries. We have seen zero occurrences of the issue.
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall