Quality Assurance of DRC deck by QA Cell Methodology and Automation using Cadence Skill
DescriptionProcess Design Kit is used within the semiconductor industry to model a fabrication process for the tools used to design an integrated circuit. These set of files is provided by foundry and is used by designer to design, simulate and verify the IP before tape-out.
Quality of the PDK is critical or if compromised, it leads to silicon failure which returns as a huge loss to the company.
DRC is very important sign-off check and as the technology nodes tends to become smaller, the complexity and the criticality of each rule becomes higher. Currently various regression pattern-based techniques are used widely to verify the DRC deck.
QAcell methodology refers to the creation of exhaustive small layouts that represents both fail and pass configurations , for every rule mentioned in the DRM and verifying the functionality of the DRC deck separately for each rule.
It is ensured that the DRC is aligned to the DRM and if there are any discrepancy then it is captured and corrected before the PDK is released ensuring less number of bugs propagated to design check. User efficiency can be increased by using SKILL automation reducing the time factor by 5 times.
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall