Layout Proximity Effect On Interconnect Capacitance
DescriptionThe characterization and modeling of interconnect resistance and capacitance is an important part of circuit design and analysis flow. Many back-end EDA tools (e.g., timing and closure tools) use the resistance and capacitance components generated by layout parasitic extraction tools. While the modeling of interconnect resistance is relatively easy, the modeling of interconnect capacitance remains a challenge over the past 30 years. Great progress has been made over the past 30 years. On the other hand, there are layout proximity effects on interconnect capacitance (which is similar to proximity effects on transistor performance). EM field solvers can capture these secondary layout effects through careful design of test cases. But these secondary layout effects on interconnect capacitance are mostly ignored by EDA parasitic extraction (PEX) tools, circuit designers, and/or semiconductor process engineers so far. We discuss several layout proximity effects on interconnect capacitance in this presentation. Foundries and EDA PEX tools must start to capture these secondary layout effects. Incorporation of these effects in EDA tools through highly efficient algorithms will benefit high frequency circuit designs.
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall