EM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs
DescriptionInterconnect Reliability is of growing importance with shrink in process, tighten in margins for Signal & Power EM due to lesser area, stricter design rules, increasing clock frequency and transistor count and also accommodate multiple voltage rails yet ensure robust Power grid design to meet IR-drop spec. Analog Mixed Signal design adds further challenges to the methodology due to mixed design style, analog-digital interaction and hand drawn custom layouts. Typically vector based spice simulation driven dynamic analysis is executed for EM/IR analysis of analog building blocks. However, to do the same at custom top level is often challenging due to growing size of the design, presence of custom digital content along with analog building blocks and hence difficulty in creating simulation testbenches with desired coverage. This often leads to feasibility issue in running tool based analysis henceforth relying on manual review, spot check etc which are riskprone. This paper explains a novel vectorless approach as the way out which leveraged Digital ASIC tools to architect a signoff methodology in mixed signal space for custom top level hierarchies. It helped to close the analysis 20x faster and carries potential of new industry standard.
Engineering Track Poster
TimeWednesday, July 12th5:29pm - 5:30pm PDT
LocationLevel 2 Exhibit Hall