Presentation
Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis
DescriptionMultiple threshold voltage (Vt) transistors are required for efficient tradeoff between power and timing. Different masks are used between different Vt device classes or between nmos (N) and pmos (P) devices making them not fully correlated among each other, and therefore leading to Vt or P/N mis-tracking phenomena impacting design's timing. Traditional library characterization methodologies generally set all device parameters to their corner values to determine library process corners for each Vt type without considering mis-tracking among different Vt and P/N transistors.
Applying traditional min/max timing derates on launch and capture paths can be too pessimistic and can cost additional PPA yet ignoring the effect may lead to severe timing problems causing chip failure.
In this work, we capture design timing impacts of Vt and P/N mis-tracking effects by using device skew analysis by enumerating all min/max device parameter combinations across Vt classes and P/N devices within a timing path and finding the mis-tracking combination leading to worst timing slack. Additionally, we use fast Monte Carlo analysis to further reduce pessimism. Using device skew analysis we were able to reduce the number of STA runs by more than 3x while improving productivity and design's robustness across multiple Vt corners in 5nm and below technologies.
Applying traditional min/max timing derates on launch and capture paths can be too pessimistic and can cost additional PPA yet ignoring the effect may lead to severe timing problems causing chip failure.
In this work, we capture design timing impacts of Vt and P/N mis-tracking effects by using device skew analysis by enumerating all min/max device parameter combinations across Vt classes and P/N devices within a timing path and finding the mis-tracking combination leading to worst timing slack. Additionally, we use fast Monte Carlo analysis to further reduce pessimism. Using device skew analysis we were able to reduce the number of STA runs by more than 3x while improving productivity and design's robustness across multiple Vt corners in 5nm and below technologies.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:36pm - 5:38pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V