An Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
DescriptionGPGPU is commonly used in data-center, AI and high performance computing systems. To achieve higher computing performance and bandwidth, the growing current demand of GPGPU makes the power delivery network(PDN) design become more and more challenging: 1) Increasing cores and operating frequency generate higher TDP and larger di/dt; 2) Lower operating voltage resulted in tighten voltage droop SPEC; 3) More AI applications to support increased the complexity of worst current scenario sign off for system level power integrity analysis; 4) Increasing signal routing in board and package squeezed up physical design room for PDN design. In system level power integrity analysis, a target impedance in frequency domain is frequently used to design PDN. However, this method requires to flatten the PDN impedance in a wide range frequency, which will cause overdesign problem and not feasible to address above challenges.

In this paper, we proposed an accurate system level transient voltage droop simulation methodology for high performance GPGPU PDN design and optimization. The accuracy of voltage droop mainly depends on current profiling and accurate PDN modeling. Firstly, we developed an accurate and efficient current profiling flow for system level voltage droop simulation. We used the gate level current profile to achieve result accuracy and take the advantage of RTL level current profile generated from Ansys PowerArtist tool to improve simulation efficiency. With combined usage of gate level/RTL level current, we're able to shift PDN design to RTL design stage and to do quick iteration with accuracy. Secondly, we presented a novel PDN power model extraction methodology with board, socket and package design merged. This way enables us to consider accurate socket model impact compared with traditional separate model extraction way. Lastly, we did voltage droop lab measurement to verify the accuracy of simulation flow. The simulated voltage droop is well correlated with the measurement result.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:10pm - 5:12pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design