Electrical Analysis using Hierarchical Approach On Ultra Large Designs
DescriptionChips are getting monstrous with evolving technologies. IR Sign-off is challenging for designers with huge node counts and limited computed resources.
Traditional distributive processing runs require large amounts of memory, have long runtime, and are practically not feasible for huge designs (~400 million instances). The current solution is a cookie cutter approach to divide the design into multiple partitions for sign-off which leads to loss of accuracy.
Solution of Hierarchical Modeling with Distributed Parallel Processing EMIR reduce runtime and memory with acceptable accuracy compared to full flat run
Engineering Track Poster
TimeWednesday, July 12th5:27pm - 5:29pm PDT
LocationLevel 2 Exhibit Hall