Novel Hierarchical IREM Sign-off Flow using ROM
DescriptionIREM sign-off run time is getting increase as node count increases due to node scaling. Top-level IREM analsys takes more than a day and sometimes over a week because it is required to have all sub-blocks flattened and run at once. To overcome run time hurdle, this presentation introduces the compact sub-block modeling method in Ansys's RedHawk-SC, as known as ROM, to result in more accurate IREM values in top-level fullchip IREM analysis while reducing node count by substituting sub-block to compact models to overcome runtime hurdles. In addition, this presentation introduces the accurate block-level IREM sign-off methodology by measuring node voltages at nodes on the connecting layer between the top and sub-block from the top-level fullchip analysis with ROM, and feeding back the sub-block sign-off run as voltage sources.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:47pm - 5:49pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design