Presentation
A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
DescriptionAs the modern ultra-large FinFet based SoCs are getting more complex and increasing in size close to the reticle limit , one of the key signoff flows of power-integrity is becoming increasingly complex.
In this paper we demonstrate a novel hierarchical methodology which enables bottoms-up model based approach to help leverage the hierarchical nature of these SoCs and their subsystems.
This methodology not only helps reduce the overall complexity but also enables true top-down & bottom-up flow. The accuracy of the flows are compared to the traditional flat analysis which is very resource intensive as well as very complex to execute at the top-level stages of design closure.
In this paper we demonstrate a novel hierarchical methodology which enables bottoms-up model based approach to help leverage the hierarchical nature of these SoCs and their subsystems.
This methodology not only helps reduce the overall complexity but also enables true top-down & bottom-up flow. The accuracy of the flows are compared to the traditional flat analysis which is very resource intensive as well as very complex to execute at the top-level stages of design closure.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:06pm - 5:07pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V