Novel Chip-Package-System thermal analysis with RTL Power
DescriptionWith the evolution of new technologies and new applications, the chip capacity and complexity are constantly increasing. Meanwhile 2.5D and 3D package make the design more complex. Increasing chip power and packaging complexity make chip thermal design more and more challenging.

A thermal model of the chip can be used as a heat source to do chip-level thermal simulation. But the model is typically based on gate netlist and generated by the backend tools. It can not be used to do transient thermal analysis and guide thermal optimization in the early design stage.

RTL power thermal flow can do power analysis in RTL stage and generate power curve as an output. These power curves can be used as the power source in system level thermal simulation. In addition the capacity and performance of RTL power analysis provides the possibility to analyze long real application scenarios of large design, desrisking the design and schedule from issues uncovered late.

In this paper, we propose a novel flow to analyze RTL power for multi dies or multi blocks and then thermal simulation based on RTL power. The thermal analysis result can be used to guide design in RTL stage.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:46pm - 5:47pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design