Bridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics Designs
DescriptionWith shrinking process node effects and power-efficient low voltage operations, voltage droop contributes significantly to the performance-per-watt-metric. Graphics IP utilization is as high as 80+%, along with >2 GHz clocks and affected high power grid resistance per um with the latest process nodes, which results in high signoff convergence effort. Traditional signoff of siloing timing and IR drop, limits the capability to accurately reflect post-silicon. Timing-aware IR modeling and IR aware static timing analysis (STA) helps bridge these gaps. This paper is a two-part overview of how we are signing off IR and timing as a single signoff. This paper starts with a study of the correlation between timing slacks and voltage droop. The first part goes over the correlation data to develop a timing modeling methodology which gives coverage for static IR drop as timing slacks instead of voltage guard band targets in the Redhawk® tool. The second part covers about using tool native features of dynamic IR voltage drop data from Redhawk-Seascape® transferred into PrimeTime® STA to adjust timing slacks. With a timing aware IR implementation, we were able to reduce our IR drop limit by 50 a neglgible gate count increase. With IR-aware STA we are exchanging 500 IR violations with 40 timing violations resulting in a 10x exchange rate. Because of the maturity of timing ECO tools compared to IR ECO methods and the ability to isolate the timing fixes to non-IR sensitive instance, we are reducing the IR convergence effort. This paper also contains information on future development activities that we have planned to establish a fully integrated IR-STA signoff when moving into the sub-nanometer/Angstrom era
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:19pm - 5:21pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design