Integration of Intel Thermal Model with Design-for-Reliability Flow
DescriptionIn advanced technology nodes, thermal dissipation at transistor and interconnect level becomes more isolated. As technology scaling pushes power density higher, risk of local thermal effect is greater for device aging and electromigration impact. Here we present an integrated Reliability verification (RV) flow with specific thermal model for Intel 3 (FinFET technology) and Intel 20A/18A (RibbonFET) processes. Compared to previous methodology where Intel provides a thermal engine for EDA tools, this flow implements natively the local thermal models in EDA tools while preserving the strong layout sensitivity unique to advanced process nodes. We share examples of device and interconnect thermal coupling and demonstrate design usage with accurate and efficient thermal analysis on large design database. We also share the improvement in the ease-of-use aspect of RV design feedback. Customers on Intel foundry nodes can enjoy independent access to thermal simulation capability while meeting reliability requirement.
Engineering Track Poster
TimeWednesday, July 12th5:38pm - 5:39pm PDT
LocationLevel 2 Exhibit Hall