Presentation
Pre-Silicon Power Side-channel Security Verification for Crypto IPs
DescriptionSummary
• Pre-silicon security verification flow is essential for semiconductor industry
• Proposal of EDA flow for side-channel trace generation, alignment and analytics
• Scalable performance and comprehensive coverage of leakage to mitigate power side-channel vulnerabilities
• Pre-silicon security verification flow is essential for semiconductor industry
• Proposal of EDA flow for side-channel trace generation, alignment and analytics
• Scalable performance and comprehensive coverage of leakage to mitigate power side-channel vulnerabilities
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V