Presentation
Pre-Silicon Power Side-channel Security Verification for Crypto IPs
DescriptionSummary
• Pre-silicon security verification flow is essential for semiconductor industry
• Proposal of EDA flow for side-channel trace generation, alignment and analytics
• Scalable performance and comprehensive coverage of leakage to mitigate power side-channel vulnerabilities
• Pre-silicon security verification flow is essential for semiconductor industry
• Proposal of EDA flow for side-channel trace generation, alignment and analytics
• Scalable performance and comprehensive coverage of leakage to mitigate power side-channel vulnerabilities
Event Type
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
TimeMonday, July 10th5:08pm - 5:16pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP