Presentation
Comprehensive, and Automated IP and SoC Connectivity Verification Sign Off using Formal DV Technique
DescriptionSoC and IP Design Cycle time reduction results in cost savings, early samples to customers, and ultimately capturing the market at the right time.
It becomes incumbent to verify Connectivity within a SoC, across SoCs (with add on or cut down features) with a reduced cycle time and IPs to IOs (handled by the IO Controller)
It is important to look for a re-usable, automated, and scalable solution to tackle connectivity verification, and simulation-based approach is quite cumbersome in this regard
This gives rise to two verification methodologies that expedites Connectivity Verification - Reverse Connectivity & IO PinMuxing DV
The motivation is to come-up with a methodology to prove Connectivity Correctness comprehensively across SoC releases and across SoC designs in a platform (with minimal changes)
The proposed flow ensures that connectivity of feature set from Proven Silicon Design and that of the new SoC (spin device) is unaffected with incremental updates
It becomes incumbent to verify Connectivity within a SoC, across SoCs (with add on or cut down features) with a reduced cycle time and IPs to IOs (handled by the IO Controller)
It is important to look for a re-usable, automated, and scalable solution to tackle connectivity verification, and simulation-based approach is quite cumbersome in this regard
This gives rise to two verification methodologies that expedites Connectivity Verification - Reverse Connectivity & IO PinMuxing DV
The motivation is to come-up with a methodology to prove Connectivity Correctness comprehensively across SoC releases and across SoC designs in a platform (with minimal changes)
The proposed flow ensures that connectivity of feature set from Proven Silicon Design and that of the new SoC (spin device) is unaffected with incremental updates
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V