Presentation
Automatic Check Generation for Reset States From Design Documents
DescriptionMost systems have various reset modes.
Hard reset/full power cycle/cold boot will clear the system but also remove the states and information for tracing why the reset needed in the first place.
Warm reset is when the system only reset some states and assists on keeping the machine partially up; also maintains some information prior to the warm reset.
Across various industries, a component of a system that maintains system monitoring and configurations control referred to as Intelligent Platform Management Interface (IPMI) allows various method of reset and information collection and management.
A bug in a component of IPMI can be traced to some register being only reset in full power cycle and not on warm reset.
This presentation shows the detail flow of how automatically generate System Verilog assertions(SVA) for both verification by simulation and formal verification from design documentation.
Also, to harvest the registers from RTL and check the presence in the design documentation.
Hard reset/full power cycle/cold boot will clear the system but also remove the states and information for tracing why the reset needed in the first place.
Warm reset is when the system only reset some states and assists on keeping the machine partially up; also maintains some information prior to the warm reset.
Across various industries, a component of a system that maintains system monitoring and configurations control referred to as Intelligent Platform Management Interface (IPMI) allows various method of reset and information collection and management.
A bug in a component of IPMI can be traced to some register being only reset in full power cycle and not on warm reset.
This presentation shows the detail flow of how automatically generate System Verilog assertions(SVA) for both verification by simulation and formal verification from design documentation.
Also, to harvest the registers from RTL and check the presence in the design documentation.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V