Presentation
Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module
DescriptionSeveral emerging markets require complex functionality with platform flexibility in an SoC. Many analog power delivery, analog signal path and RF signal chain functions can benefit from existing ICs in older technology. MCM can provide a means for quicker time to market, and help focus on development of differentiating new functions, benefiting from newer technology nodes with higher density of integration, lower power and higher performance.
Current MCM technologies involve independent development, verification and validation of different chips or dies. This involves manual MCM integration, due to lack of environment and capability for integrated MCM level verification for complex low power mixed-signal SoCs, resulting in late findings of MCM package level integration issues at LVS stage can throw surprises. Analog on Top integration methods for analog centric ICs lessen some of these concerns due to a unified schematic frontend. Hence there is a need for MCM level LVS for equivalence between schematic and final IC layout and MCM package physical design, though this can be used only at a very late design stage.
This work presents a novel solution for an automated MCM netlist generation from package level integration information (ARC), to avoid a need for MCM level LVS at mature design stages. This flow generates different MCM netlist abstractions needed for early frontend verification including low power AMS co-sim. and LVS, Verilog and SPICE netlists & Power intent (CPF and UPF).
Current MCM technologies involve independent development, verification and validation of different chips or dies. This involves manual MCM integration, due to lack of environment and capability for integrated MCM level verification for complex low power mixed-signal SoCs, resulting in late findings of MCM package level integration issues at LVS stage can throw surprises. Analog on Top integration methods for analog centric ICs lessen some of these concerns due to a unified schematic frontend. Hence there is a need for MCM level LVS for equivalence between schematic and final IC layout and MCM package physical design, though this can be used only at a very late design stage.
This work presents a novel solution for an automated MCM netlist generation from package level integration information (ARC), to avoid a need for MCM level LVS at mature design stages. This flow generates different MCM netlist abstractions needed for early frontend verification including low power AMS co-sim. and LVS, Verilog and SPICE netlists & Power intent (CPF and UPF).
Event Type
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
TimeMonday, July 10th5:24pm - 5:32pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP