Presentation
Unified Design Verification Flow for Pre-Silicon SoC Power Estimation And Achieving Post-Silicon Correlation to Customer Sampling
DescriptionMajority of semiconductor customers building applications on multi core designs with integrated RF work with a power budget. The SoC's power budget is decided during the architecture phase based on empirical data which may vary at the end of Physical Design cycle. After the SoC is fabricated, its critical to correlate the accuracy and range of power per block and sample devices to customers as per the power budget committed.
SoC's real time power consumption number is decided by the Software code which can be developed near design phase closure after the device is received. So, currently there is no direct methodology to measure power on silicon at a large scale, unlike structural tests done on tester.
This presentation talks about the role of DV in the new methodology established for power correlation between Pre-SI estimates to Post-SI power measurement and how to screen devices on ATE to sample the right devices within the power budget limits.
Keywords: Power estimation, Power correlation, Design Verification, ATE Screening
SoC's real time power consumption number is decided by the Software code which can be developed near design phase closure after the device is received. So, currently there is no direct methodology to measure power on silicon at a large scale, unlike structural tests done on tester.
This presentation talks about the role of DV in the new methodology established for power correlation between Pre-SI estimates to Post-SI power measurement and how to screen devices on ATE to sample the right devices within the power budget limits.
Keywords: Power estimation, Power correlation, Design Verification, ATE Screening
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V