Presentation
The Benefits of Formal Signoff on New and Mature Designs
DescriptionThe use of formal verification has been increasing thanks to the widespread adoption of formal applications and assertion-based formal verification. However, to replace block-level simulation and find bugs early in the design process, we must reliably advance formal verification beyond focusing on a handful of properties to thoroughly verify all block-level design behaviors, i.e., formal signoff.
An end-to-end formal testbench allows RTL designers and formal engineers to work concurrently early in the design cycle, finishing the RTL functionality and formally verifying the block's behaviors before integrating it into the top-level simulation environment confidently.
Furthermore, given that today's formal tools cannot close the end-to-end checkers required to verify complex IP blocks, we must rely on methodology to tackle design complexity in a way that allows the formal tool to converge reliability. This paper elaborates on the end-to-end formal testbench methodology and discusses how we can reduce the complexity of the design with decomposition and abstraction techniques.
An end-to-end formal testbench allows RTL designers and formal engineers to work concurrently early in the design cycle, finishing the RTL functionality and formally verifying the block's behaviors before integrating it into the top-level simulation environment confidently.
Furthermore, given that today's formal tools cannot close the end-to-end checkers required to verify complex IP blocks, we must rely on methodology to tackle design complexity in a way that allows the formal tool to converge reliability. This paper elaborates on the end-to-end formal testbench methodology and discusses how we can reduce the complexity of the design with decomposition and abstraction techniques.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V