Presentation
Automated Analog Model Generation for High Quality Verification using Event Driven Simulators
DescriptionThe paper focuses on the method to reduce the analog behavioural model (BMOD) creation and validation effort and cycle time by automating the process of model generation. To accomplish the same MODELZEN, an automatic model generator for analog circuits that can translate any circuit into an equivalent SystemVerilog model, is utilised. The generated model can be simulated entirely in an event driven simulator. It results in potential descoping most of SoC level AMS co-sim. by utilizing the higher fidelity and accuracy of BMODs resultant from underlying model generation flow without impact to runtime of current state-of-the art manually created BMODs. Thus speeds up the process of verification and advances it by several months for a low power mixed-signal SoC. Development. Additionally, we showcase a pioneering capability of performing analog defect simulation using defect simulators.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:15pm - 5:16pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V