Design Verification Waveform Analysis through Machine Learning Solution
DescriptionEquivalence checking in analog continuous state space is a persistent challenge in analog and mixed-signal verification. In analog simulations continuous space of circuit response leads do an indefinite signal flow from input to output. As a result, developing a flow for equivalence checking between actual and expected behavior is still an elusive challenge. A golden reference model for every analog timestep is needed for accurate and thorough equivalence checking. This requires a radical approach. Development of probabilistically approximately correct (PAC) machine learning (ML) model using design verification simulation data which becomes the golden reference model is our solution.
ML model built based on simulation data "can automatically generate golden reference data for new cases and can be used to flag outliers and bugs" leading to an appreciable reduction in time and human effort with a significant improvement of quality in the verification process.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design